digtalclk.map.qmsg

用Altera公司的QuartusII编写的电子钟程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Oct 29 21:15:15 2007 " "Info: Processing started: Mon Oct 29 21:15:15 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off digtalclk -c digtalclk " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off digtalclk -c digtalclk" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "digtalclk.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file digtalclk.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 digtalclk " "Info: Found entity 1: digtalclk" {  } { { "digtalclk.bdf" "" { Schematic "D:/Study/大4/近代电子学试验QuartusII/digtalclk/digtalclk.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clock.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bin2seg.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file bin2seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2seg " "Info: Found entity 1: bin2seg" {  } { { "bin2seg.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/bin2seg.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "skey.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file skey.v" { { "Info" "ISGN_ENTITY_NAME" "1 skey " "Info: Found entity 1: skey" {  } { { "skey.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/skey.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "digtalclk " "Info: Elaborating entity \"digtalclk\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock clock:inst1 " "Info: Elaborating entity \"clock\" for hierarchy \"clock:inst1\"" {  } { { "digtalclk.bdf" "inst1" { Schematic "D:/Study/大4/近代电子学试验QuartusII/digtalclk/digtalclk.bdf" { { 80 400 544 208 "inst1" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 clock.v(34) " "Warning: Verilog HDL assignment warning at clock.v(34): truncated value with size 6 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 34 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 clock.v(35) " "Warning: Verilog HDL assignment warning at clock.v(35): truncated value with size 6 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 35 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 clock.v(36) " "Warning: Verilog HDL assignment warning at clock.v(36): truncated value with size 5 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 36 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 clock.v(37) " "Warning: Verilog HDL assignment warning at clock.v(37): truncated value with size 5 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 37 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 clock.v(41) " "Warning: Verilog HDL assignment warning at clock.v(41): truncated value with size 6 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 41 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 clock.v(42) " "Warning: Verilog HDL assignment warning at clock.v(42): truncated value with size 6 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 42 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "7 4 clock.v(43) " "Warning: Verilog HDL assignment warning at clock.v(43): truncated value with size 7 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 43 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "7 4 clock.v(44) " "Warning: Verilog HDL assignment warning at clock.v(44): truncated value with size 7 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 44 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 clock.v(48) " "Warning: Verilog HDL assignment warning at clock.v(48): truncated value with size 5 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 48 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 clock.v(49) " "Warning: Verilog HDL assignment warning at clock.v(49): truncated value with size 5 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 49 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 clock.v(50) " "Warning: Verilog HDL assignment warning at clock.v(50): truncated value with size 6 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 50 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 clock.v(51) " "Warning: Verilog HDL assignment warning at clock.v(51): truncated value with size 6 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 51 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "14 4 clock.v(55) " "Warning: Verilog HDL assignment warning at clock.v(55): truncated value with size 14 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 55 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "14 4 clock.v(56) " "Warning: Verilog HDL assignment warning at clock.v(56): truncated value with size 14 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 56 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "14 4 clock.v(57) " "Warning: Verilog HDL assignment warning at clock.v(57): truncated value with size 14 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 57 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "14 4 clock.v(58) " "Warning: Verilog HDL assignment warning at clock.v(58): truncated value with size 14 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 58 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 clock.v(62) " "Warning: Verilog HDL assignment warning at clock.v(62): truncated value with size 6 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 62 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 clock.v(63) " "Warning: Verilog HDL assignment warning at clock.v(63): truncated value with size 6 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 63 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 clock.v(64) " "Warning: Verilog HDL assignment warning at clock.v(64): truncated value with size 5 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 64 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 clock.v(65) " "Warning: Verilog HDL assignment warning at clock.v(65): truncated value with size 5 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 65 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(75) " "Warning: Verilog HDL assignment warning at clock.v(75): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 75 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(76) " "Warning: Verilog HDL assignment warning at clock.v(76): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 76 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(77) " "Warning: Verilog HDL assignment warning at clock.v(77): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 77 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(78) " "Warning: Verilog HDL assignment warning at clock.v(78): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 78 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 clock.v(82) " "Warning: Verilog HDL assignment warning at clock.v(82): truncated value with size 6 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 82 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 clock.v(83) " "Warning: Verilog HDL assignment warning at clock.v(83): truncated value with size 6 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 83 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 clock.v(84) " "Warning: Verilog HDL assignment warning at clock.v(84): truncated value with size 5 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 84 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 clock.v(85) " "Warning: Verilog HDL assignment warning at clock.v(85): truncated value with size 5 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 85 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(90) " "Warning: Verilog HDL assignment warning at clock.v(90): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 90 0 0 } }  } 0}