uart_clk.fit.qmsg

Uart port 是一段不错的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 11 19:41:49 2006 " "Info: Processing started: Mon Dec 11 19:41:49 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off uart_clk -c uart_clk " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off uart_clk -c uart_clk" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "uart_clk EP20K200EQC240-3 " "Info: Selected device EP20K200EQC240-3 for design \"uart_clk\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "sys_clock automatically " "Info: Promoted cell \"sys_clock\" to global signal automatically" {  } {  } 0 0 "Promoted cell \"%1!s!\" to global signal %2!s!" 0 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "divide_by_13:divide_13\|temp\[3\] automatically " "Info: Promoted cell \"divide_by_13:divide_13\|temp\[3\]\" to global signal automatically" {  } {  } 0 0 "Promoted cell \"%1!s!\" to global signal %2!s!" 0 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "divide_by_256:divide_256\|clock~34 automatically " "Info: Promoted cell \"divide_by_256:divide_256\|clock~34\" to global signal automatically" {  } {  } 0 0 "Promoted cell \"%1!s!\" to global signal %2!s!" 0 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "rest automatically " "Info: Promoted cell \"rest\" to global signal automatically" {  } {  } 0 0 "Promoted cell \"%1!s!\" to global signal %2!s!" 0 0}
{ "Info" "IFIT_FIT_ATTEMPT" "1 Mon Dec 11 2006 19:41:57 " "Info: Started fitting attempt 1 on Mon Dec 11 2006 at 19:41:57" {  } {  } 0 0 "Started fitting attempt %1!d! on %2!s! at %3!s!" 0 0}
{ "Warning" "WFITAPI_FITAPI_WARNING_VPR_PERFORMANCE_MAY_DEGRADE_AS_FDI_IS_NOT_LOADED" "" "Warning: Performance of this circuit may degrade because the Fitter Delay Information is not loaded." {  } {  } 0 0 "Performance of this circuit may degrade because the Fitter Delay Information is not loaded." 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACER_ESTIMATED_ROUTING_RESOURCE_USAGE" "" "Info: Design requires the following device routing resources:" { { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_COL_FSTTRK" "0 " "Info: Overall column FastTrack interconnect = 0%" {  } {  } 0 0 "Overall column FastTrack interconnect = %1!d!%%" 0 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_ROW_FSTTRK" "0 " "Info: Overall row FastTrack interconnect = 0%" {  } {  } 0 0 "Overall row FastTrack interconnect = %1!d!%%" 0 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_COL_FSTTRK" "0 " "Info: Maximum column FastTrack interconnect = 0%" {  } {  } 0 0 "Maximum column FastTrack interconnect = %1!d!%%" 0 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_ROW_FSTTRK" "2 " "Info: Maximum row FastTrack interconnect = 2%" {  } {  } 0 0 "Maximum row FastTrack interconnect = %1!d!%%" 0 0}  } {  } 0 0 "Design requires the following device routing resources:" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.908 ns register register " "Info: Estimated most critical path is register to register delay of 4.908 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.291 ns) 0.291 ns divide_by_256:divide_256\|temp\[0\] 1 REG LAB_4_O1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.291 ns) = 0.291 ns; Loc. = LAB_4_O1; Fanout = 3; REG Node = 'divide_by_256:divide_256\|temp\[0\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "" { divide_by_256:divide_256|temp[0] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.321 ns) + CELL(2.018 ns) 2.630 ns divide_by_256:divide_256\|temp\[0\]~75 2 COMB LAB_4_O1 2 " "Info: 2: + IC(0.321 ns) + CELL(2.018 ns) = 2.630 ns; Loc. = LAB_4_O1; Fanout = 2; COMB Node = 'divide_by_256:divide_256\|temp\[0\]~75'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "2.339 ns" { divide_by_256:divide_256|temp[0] divide_by_256:divide_256|temp[0]~75 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.148 ns) 2.778 ns divide_by_256:divide_256\|temp\[1\]~72 3 COMB LAB_4_O1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.148 ns) = 2.778 ns; Loc. = LAB_4_O1; Fanout = 2; COMB Node = 'divide_by_256:divide_256\|temp\[1\]~72'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "0.148 ns" { divide_by_256:divide_256|temp[0]~75 divide_by_256:divide_256|temp[1]~72 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.148 ns) 2.926 ns divide_by_256:divide_256\|temp\[2\]~69 4 COMB LAB_4_O1 2 " "Info: 4: + IC(0.000 ns) + CELL(0.148 ns) = 2.926 ns; Loc. = LAB_4_O1; Fanout = 2; COMB Node = 'divide_by_256:divide_256\|temp\[2\]~69'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "0.148 ns" { divide_by_256:divide_256|temp[1]~72 divide_by_256:divide_256|temp[2]~69 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.148 ns) 3.074 ns divide_by_256:divide_256\|temp\[3\]~78 5 COMB LAB_4_O1 2 " "Info: 5: + IC(0.000 ns) + CELL(0.148 ns) = 3.074 ns; Loc. = LAB_4_O1; Fanout = 2; COMB Node = 'divide_by_256:divide_256\|temp\[3\]~78'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "0.148 ns" { divide_by_256:divide_256|temp[2]~69 divide_by_256:divide_256|temp[3]~78 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.148 ns) 3.222 ns divide_by_256:divide_256\|temp\[4\]~63 6 COMB LAB_4_O1 2 " "Info: 6: + IC(0.000 ns) + CELL(0.148 ns) = 3.222 ns; Loc. = LAB_4_O1; Fanout = 2; COMB Node = 'divide_by_256:divide_256\|temp\[4\]~63'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "0.148 ns" { divide_by_256:divide_256|temp[3]~78 divide_by_256:divide_256|temp[4]~63 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.148 ns) 3.370 ns divide_by_256:divide_256\|temp\[5\]~57 7 COMB LAB_4_O1 2 " "Info: 7: + IC(0.000 ns) + CELL(0.148 ns) = 3.370 ns; Loc. = LAB_4_O1; Fanout = 2; COMB Node = 'divide_by_256:divide_256\|temp\[5\]~57'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "0.148 ns" { divide_by_256:divide_256|temp[4]~63 divide_by_256:divide_256|temp[5]~57 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.148 ns) 3.518 ns divide_by_256:divide_256\|temp\[6\]~60 8 COMB LAB_4_O1 1 " "Info: 8: + IC(0.000 ns) + CELL(0.148 ns) = 3.518 ns; Loc. = LAB_4_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256\|temp\[6\]~60'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "0.148 ns" { divide_by_256:divide_256|temp[5]~57 divide_by_256:divide_256|temp[6]~60 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.390 ns) 4.908 ns divide_by_256:divide_256\|temp\[7\] 9 REG LAB_4_O1 2 " "Info: 9: + IC(0.000 ns) + CELL(1.390 ns) = 4.908 ns; Loc. = LAB_4_O1; Fanout = 2; REG Node = 'divide_by_256:divide_256\|temp\[7\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "1.390 ns" { divide_by_256:divide_256|temp[6]~60 divide_by_256:divide_256|temp[7] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.587 ns ( 93.46 % ) " "Info: Total cell delay = 4.587 ns ( 93.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.321 ns ( 6.54 % ) " "Info: Total interconnect delay = 0.321 ns ( 6.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "4.908 ns" { divide_by_256:divide_256|temp[0] divide_by_256:divide_256|temp[0]~75 divide_by_256:divide_256|temp[1]~72 divide_by_256:divide_256|temp[2]~69 divide_by_256:divide_256|temp[3]~78 divide_by_256:divide_256|temp[4]~63 divide_by_256:divide_256|temp[5]~57 divide_by_256:divide_256|temp[6]~60 divide_by_256:divide_256|temp[7] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:06 " "Info: Fitter routing operations ending: elapsed time is 00:00:06" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 11 19:42:07 2006 " "Info: Processing ended: Mon Dec 11 19:42:07 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Info: Elapsed time: 00:00:19" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}