ddr_command_timesim.nlf

一个小测试程序希望,朋友有所帮助,赶快下吧@@!!VERILOG

Release 6.2i - netgen G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

Loading device database for application netgen from file "ddr_command.ncd".
   "ddr_command" is an NCD, version 2.38, device xc2s200, package pq208, speed
-5
Loading device for application netgen from file 'v200.nph' in environment
E:/Xilinx6.1i.
Loading constraints from file "ddr_command.pcf"...
  Flattening design ...
  Flattening design completed.
  Specializing design ...
  Specializing design completed.
  Preping physical only global signals ...
  Preping design's networks ...
  Preping design's macros ...
Writing Verilog SDF file ddr_command_timesim.sdf ...
Writing Verilog netlist file ddr_command_timesim.v ...
INFO:NetListWriters:580 - If Verilog simulation is performed outside the ISE
   Project Navigator environment, please add $XILINX/verilog/src/glbl.v to the
   simulator compile and invocation commands in order to allow proper
   initialization of the design. If simulation is performed within Project
   Navigator, this will be taken care of automatically. For more information on
   compiling and performing Xilinx simulation, consult the online Synthesis and
   Simulation Design Guide:
   http://support.xilinx.com/support/software_manuals.htm 
Total memory usage is 52796 kilobytes