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VHDL 的代码
fpq.vhdl
-------------------------------------------------
--实体名：fen100
--功 能：对输入时钟进行24000分频，得到100Hz信号，
-- 作为数码显示管位扫描信号
--接 口：clk -时钟输入
-- qout-100Hz输出信号
-----------------------------
fenliwei.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
jtd.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
xzqwo.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
djs.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
xzq.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
vhdl.vhd
-- generated by newgenasym Wed Oct 29 11:37:46 2008
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity dio is
port (
A: INOUT STD_LOGIC;
K: INOUT
vhdl.vhd
-- generated by newgenasym Fri Oct 24 13:50:15 2008
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity diozener is
port (
A: INOUT STD_LOGIC;
K: IN
vhdl.vhd
-- generated by newgenasym Thu Oct 23 15:29:46 2008
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity trpnp is
port (
B: INOUT STD_LOGIC;
C: INOUT
vhdl.vhd
-- generated by newgenasym Thu Oct 23 15:22:00 2008
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity trnpn is
port (
B: INOUT STD_LOGIC;
C: INOUT