djs.vhdl

交通灯控制,在A和B方向各用数码管显示剩余的时间.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DJS is
   port(
	   clk: in std_logic;
	   AXS:in std_logic_vector(2 downto 0);
	   CNT1: out std_logic_vector(5 downto 0);
	   CNT2: out std_logic_vector(5 downto 0));
end DJS;

architecture Behavioral of DJS is
  signal count1:std_logic_vector(5 downto 0);
  signal count2:std_logic_vector(5 downto 0); 
begin
  process(AXS,clk)
  begin
  if(clk'event and clk='1') then
     if AXS="111" then
	      count1<="000000";
		 count2<="000000";
     elsif AXS="000" then
	       if count1="000000" then
		     count1<="100111";
	       else		 
	          count1<=count1-1;
		  end if;
		  if count2="00000" then
		     count2<="111011";
	       else		 
	          count2<=count2-1;
		  end if;
     elsif AXS="001" then
	       if count1="000000" then
		     count1<="010011";
	       else		 
	          count1<=count1-1;
		  end if;
		  if count2="010100" then
		     count2<="010011";
	       else		 
	          count2<=count2-1;
		  end if;
     elsif AXS="010" then
	       if count1="000000" then
		     count1<="110001";
	       else		 
	          count1<=count1-1;
		  end if;
		  if count2="000000" then
		     count2<="011101";
	       else		 
	          count2<=count2-1;
		  end if;
	elsif  AXS="011" then
	       if count1="010100" then
		     count1<="010011";
	       else		 
	          count1<=count1-1;
		  end if;
		  if count2="000000" then
		     count2<="010011";
	       else		 
	          count2<=count2-1;
		  end if;
	end if;
  end if;
	    CNT1<=count1;
	    CNT2<=count2;
  end process;
end Behavioral;