fenliwei.vhdl

交通灯控制,在A和B方向各用数码管显示剩余的时间.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FENGLIWEI is
    port(clk:in std_logic;
         cnt1:in std_logic_vector(5 downto 0);
	    cnt2:in std_logic_vector(5 downto 0);
	    age,ashi:out std_logic_vector(3 downto 0);
	    bge,bshi:out std_logic_vector(3 downto 0));
end FENGLIWEI;

architecture Behavioral of FENGLIWEI is

begin
   process(clk,cnt1)
   variable comb1:std_logic_vector(5 downto 0):="000000";
   variable comb1a,comb1b:std_logic_vector(3 downto 0);
   begin
      if(clk'event and clk='1')then
	    if(comb1<cnt1)then
		   if(comb1a=9)then 
		     comb1a:="0000";
			comb1b:=comb1b+1;
			comb1:=comb1+1;
		   else 
		     comb1a:=comb1a+1;
			comb1:=comb1+1;
		   end if;
	    else
		   age<=comb1a;
		   ashi<=comb1b;
		   comb1a:="0000";
		   comb1b:="0000";
		   comb1:="000000";
	    end if;
	end if;
   end process;
  
   process(clk,cnt2)
   variable comb2:std_logic_vector(5 downto 0):="000000";
   variable comb2a,comb2b:std_logic_vector(3 downto 0);
   begin
      if(clk'event and clk='1')then
	    if(comb2<cnt2)then
		   if(comb2a=9)then 
		     comb2a:="0000";
			comb2b:=comb2b+1;
			comb2:=comb2+1;
		   else 
		     comb2a:=comb2a+1;
			comb2:=comb2+1;
		   end if;
	     else
		   bge<=comb2a;
		   bshi<=comb2b;
		   comb2a:="0000";
		   comb2b:="0000";
		   comb2:="000000";
	    end if;
    end if;
  end process;
end Behavioral;