vhdl.vhd

Cadence_Starter_Library

-- generated by newgenasym Thu Oct 23 15:22:00 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity trnpn is
    port (    
	B:         INOUT  STD_LOGIC;    
	C:         INOUT  STD_LOGIC;    
	E:         INOUT  STD_LOGIC);
end trnpn;