vhdl.vhd

Cadence_Starter_Library

-- generated by newgenasym Wed Oct 29 11:37:46 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity dio is
    port (    
	A:         INOUT  STD_LOGIC;    
	K:         INOUT  STD_LOGIC);
end dio;