📄 jtd.vhdl
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity JTD is
Port ( clk: in std_logic;
rst : in std_logic;
AXS: out std_logic_vector(2 downto 0);
A_R : out std_logic;
A_Y : out std_logic;
A_G : out std_logic;
A_L : out std_logic;
B_R : out std_logic;
B_Y : out std_logic;
B_G : out std_logic;
B_L : out std_logic);
end JTD;
architecture Behavioral of JTD is
CONSTANT Count_MAX : INTEGER:=59;
CONSTANT Count_RY : INTEGER:=4;
CONSTANT Count_RG : INTEGER:=24;
CONSTANT Count_RL : INTEGER:=14;
CONSTANT Count_GR : INTEGER:=34;
CONSTANT Count_YR : INTEGER:=4;
CONSTANT Count_LR : INTEGER:=14;
TYPE LIGHT_STATE IS (RR,GR,YR1,YR2,LR,RG,RY1,RY2,RL);
SIGNAL CR_STATE: LIGHT_STATE;
SIGNAL NX_STATE : LIGHT_STATE;
SIGNAL CT_TIME: INTEGER RANGE 0 TO Count_Max;
SIGNAL COUNT: INTEGER RANGE 0 TO Count_Max;
begin
process(clk,rst,NX_STATE)
begin
if(rst='0') then
CR_STATE<=RR;
COUNT<=0;
elsif(clk'event and clk='1') then
if(COUNT=CT_TIME) then
CR_STATE<=NX_STATE;
COUNT<=0;
else
COUNT<=COUNT+1;
end if;
end if;
end process;
process(CR_STATE)
begin
case CR_STATE is
when RR=>
AXS<="111";
A_R<='0';A_G<='1';A_Y<='1';A_L<='1';
B_R<='0';B_G<='1';B_Y<='1';B_L<='1';
NX_STATE<=GR;
when GR=>
AXS<="000";
A_R<='1';A_G<='0';A_Y<='1';A_L<='1';
B_R<='0';B_G<='1';B_Y<='1';B_L<='1';
NX_STATE<=YR1;
CT_TIME<=Count_GR;
when YR1=>
A_R<='1';A_G<='1';A_Y<='0';A_L<='1';
B_R<='0';B_G<='1';B_Y<='1';B_L<='1';
NX_STATE<=LR;
CT_TIME<=Count_YR;
when LR=>
AXS<="001";
A_R<='1';A_G<='1';A_Y<='1';A_L<='0';
B_R<='0';B_G<='1';B_Y<='1';B_L<='1';
NX_STATE<=YR2;
CT_TIME<=Count_LR;
when YR2=>
A_R<='1';A_G<='1';A_Y<='0';A_L<='1';
B_R<='0';B_G<='1';B_Y<='1';B_L<='1';
NX_STATE<=RG;
CT_TIME<=Count_YR;
when RG=>
AXS<="010";
A_R<='0';A_G<='1';A_Y<='1';A_L<='1';
B_R<='1';B_G<='0';B_Y<='1';B_L<='1';
NX_STATE<=RY1;
CT_TIME<=Count_RG;
when RY1=>
A_R<='0';A_G<='1';A_Y<='1';A_L<='1';
B_R<='1';B_G<='1';B_Y<='0';B_L<='1';
NX_STATE<=RL;
CT_TIME<=Count_RY;
when RL=>
AXS<="011";
A_R<='0';A_G<='1';A_Y<='1';A_L<='1';
B_R<='1';B_G<='1';B_Y<='1';B_L<='0';
NX_STATE<=RY2;
CT_TIME<=Count_RL;
when RY2=>
A_R<='0';A_G<='1';A_Y<='1';A_L<='1';
B_R<='1';B_G<='1';B_Y<='0';B_L<='1';
NX_STATE<=GR;
CT_TIME<=Count_RY;
end case;
end process;
end Behavioral;
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