vhdl.vhd

Cadence_Starter_Library

-- generated by newgenasym Fri Oct 24 13:50:15 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity diozener is
    port (    
	A:         INOUT  STD_LOGIC;    
	K:         INOUT  STD_LOGIC);
end diozener;