代码搜索：VHDL
找到约 10,000 项符合「VHDL」的源代码
代码结果 10,000
www.eeworm.com/read/453446/7420368
vhd vhdl code1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ffT IS
PORT(T,CLK1,RESET:IN BIT;
Q,QINV:OUT BIT);
END ffT;
ARCHITECTURE behav OF ffT IS
SIGNAL S:BIT;
BEGIN
PROCESS
BEGIN
WAIT UNTIL CLK1='
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bak vhdl code1.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ffT IS
PORT(T,CLK1,RESET:IN BIT;
Q,QINV:OUT BIT);
END ffT;
ARCHITECTURE behav OF ffT IS
SIGNAL S:BIT;
BEGIN
PROCESS
BEGIN
WAIT UNTIL CLK='1
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vhd vhdl code1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY comp4b IS
PORT(A,B:IN BIT_VECTOR(3 DOWNTO 0);
F1,F2,F3:OUT BIT);
END ENTITY;
ARCHITECTURE behav OF comp4b IS
BEGIN
PROCESS(A,B)
BEGIN
IF(
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bak vhdl code1.bak
VHDL Code: Behavioral model:
LIBRARY IEEE;//standard library
USE IEEE.STD_LOGIC_1164.ALL;//importing the library.
//entity declaration.
ENTITY comp4b IS
PORT(A,B:IN BIT_VECTOR(3 DOWNTO 0);
F1,F2
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bak vhdl code7.bak
library ieee;use ieee.std_logic_1164.all; entity MUX is port( A: in std_logic; B: in std_logic; S: in std_logic; Z: out std_logic );end MUX; architecture main of MUX isbegin with S select Z
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vhd vhdl code7.vhd
library ieee;use ieee.std_logic_1164.all; entity MUX is port( A: in std_logic; B: in std_logic; S: in std_logic; Z: out std_logic );end MUX; architecture main of MUX isbegin with S select Z
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vhd vhdl code2.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dec24d IS
PORT(A,B,EN_L:IN BIT;
Q0,Q1,Q2,Q3:OUT BIT);
END ENTITY;
ARCHITECTURE dataflow OF dec24d IS
BEGIN
Q0
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bak vhdl code2.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dec24d IS
PORT(A,B,EN_L:IN BIT;
Q0,Q1,Q2,Q3:OUT BIT);
END ENTITY;
ARCHITECTURE dataflow OF dec24d IS
BEGIN
Q0
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vhd vhdl code1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;//standard library packages
ENTITY fullsubs IS
PORT(A,B,BORIN: IN BIT;
DIFF,BOR:OUT BIT); );//input and output declaration
END fullsubs;
ARCHITECTURE st
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bak vhdl code1.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;//standard library packages
ENTITY fullsubs IS
PORT(A,B,BORIN: IN BIT;
DIFF,BOR:OUT BIT); );//input and output declaration
END fullsubs;
ARCHITECTURE st