vhdl code1.bak

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new d

VHDL Code: Behavioral model:
LIBRARY IEEE;//standard library
USE IEEE.STD_LOGIC_1164.ALL;//importing the library.
//entity declaration.
ENTITY comp4b IS
PORT(A,B:IN BIT_VECTOR(3 DOWNTO 0);
F1,F2,F3:OUT BIT);//inputs and outputs.
END ENTITY; //end of entity declaration.
ARCHITECTURE behav OF comp4b IS
BEGIN
PROCESS(A,B)//sensitivity list.
BEGIN
IF(A(3)='0' AND B(3)='1')THEN F3<='1';F2<='0';F1<='0';
ELSIF(A(3)='1' AND B(3)='0')THEN F1<='1';F2<='0';F3<='0';
ELSE
IF(A(2)='0' AND B(2)='1')THEN F3<='1';F2<='0';F1<='0';
ELSIF(A(2)='1' AND B(2)='0')THEN F1<='1';F2<='0';F3<='0';
ELSE
IF(A(1)='0' AND B(1)='1')THEN F3<='1';F2<='0';F1<='0';
ELSIF(A(1)='1' AND B(1)='0')THEN F1<='1';F2<='0';F3<='0';
ELSE
IF(A(0)='0' AND B(0)='1')THEN F3<='1';F2<='0';F1<='0';
ELSIF(A(0)='1' AND B(0)='0')THEN F1<='1';F2<='0';F3<='0';
ELSE
F2<='1';F1<='0';F3<='0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END behav;//end of architecture.