vhdl code7.bak

来自「d flip flop t flip flop counter mux usin」· BAK 代码 · 共 2 行

library ieee;use ieee.std_logic_1164.all; entity MUX is	port(		A: in std_logic;		B: in std_logic;		S: in std_logic;		Z: out std_logic	);end MUX; architecture main of MUX isbegin	with S select Z <= A when '0', B when '1';end main;