vhdl code1.vhd

来自「d flip flop t flip flop counter mux usin」· VHDL 代码 · 共 22 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;//standard library packages
ENTITY fullsubs IS
PORT(A,B,BORIN: IN BIT;
DIFF,BOR:OUT BIT); );//input and output declaration
END fullsubs;
ARCHITECTURE struc OF fullsubs IS
COMPONENT halfsubd //basic component declarations
PORT(A,B:IN BIT;
DIFF,BOR:OUT BIT);
END COMPONENT;
COMPONENT or2bit
PORT(A,B:IN BIT;C:OUT BIT);
END COMPONENT;
SIGNAL BOR1,BOR2,DIFF1:BIT;
BEGIN//mapping
HS1:halfsubd PORT MAP(A,B,DIFF1,BOR1);
HS2:halfsubd PORT MAP(DIFF1,BORIN,DIFF,BOR2);
O1:or2bit PORT MAP(BOR1,BOR2,BOR);
END struc;