vhdl code1.vhd

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new d

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ffT IS
PORT(T,CLK1,RESET:IN BIT;
Q,QINV:OUT BIT);
END ffT;
ARCHITECTURE behav OF ffT IS
SIGNAL S:BIT;
BEGIN
PROCESS
BEGIN
WAIT UNTIL CLK1='1' AND CLK1 'EVENT;
IF(RESET='0')THEN S<='0';
ELSIF T='1' THEN S<=NOT S;
END IF;
END PROCESS;
Q<=S;
QINV<=NOT S;
END behav;
entity AND2 is
port(
x : in bit;
y : in bit;
z : out bit
);
end AND2;
architecture behav1 of AND2 is
begin
Z<= x and y; --Signal Assignment Statement
end behav1;
entity OR2 is
port(
x1: in bit;
y1 : in bit;
z1 : out bit
);
end OR2;
architecture behav2 of OR2 is
begin
Z1 <= x1 or y1; --Signal Assignment Statement
end behav2;
entity mod5 is
port(
const_input,clk:in BIT;
c1,c2,c3,c_1,c_2,c_3:out BIT);
end mod5;
architecture structure of mod5 is
component ffT
port(T,CLK1,RESET:IN BIT;
Q,QINV:OUT BIT);
end component;
component AND2 
port(
x : in bit;
y : in bit;
z : out bit
);
end component;
component OR2 
port(
x1: in bit;
y1 : in bit;
z1 : out bit
);
end component;
signal temp,xyz:bit;
begin
a1 : AND2 port map(x=>c_1,y=>c_2,z=>temp);
a2 : OR2 port map(x1=>c_3,y1=>temp,z1=>xyz);
t1 : ffT port map(const_input,clk,xyz,c1,c_1);
t2 : ffT port map(T=>const_input,CLK1=>c1,RESET=>xyz,Q=>c2,QINV=>c_2);
t3 : ffT port map(T=>const_input,CLK1=>c2,RESET=>xyz,Q=>c3,QINV=>c_3);

end structure;