vhdl code1.bak

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new d

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ffT IS
PORT(T,CLK1,RESET:IN BIT;
Q,QINV:OUT BIT);
END ffT;
ARCHITECTURE behav OF ffT IS
SIGNAL S:BIT;
BEGIN
PROCESS
BEGIN
WAIT UNTIL CLK='1' AND CLK 'EVENT;
IF(RESET='0')THEN S<='0';
ELSIF T='1' THEN S<=NOT S;
END IF;
END PROCESS;
Q<=S;
QINV<=NOT S;
END behav;
entity AND2 is
port(
x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC
);
end AND2;
architecture behav1 of AND2 is
begin
Z<= x and y; --Signal Assignment Statement
end behav1;
entity OR2 is
port(
x1: in STD_LOGIC;
y1 : in STD_LOGIC;
z1 : out STD_LOGIC
);
end OR2;
architecture behav1 of OR2 is
begin
Z1 <= x1 or y1; --Signal Assignment Statement
end behav1;
entity mod5 is
port(
const_input,clk:in std_logic;
c1,c2,c3,c_1,c_2,c_3:out std_logic);
end mod5;
architecture structure of mod5 is
component fft
port(T,CLK1,RESET:IN BIT;
Q,QINV:OUT BIT);
end fft;
component AND2 
port(
x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC
);
end component;
component OR2 
port(
x1: in STD_LOGIC;
y1 : in STD_LOGIC;
z1 : out STD_LOGIC
);
end component;
signal temp,xyz:std_logic;
begin
fft port map(const_input,clk1,xyz,c1,c_1);
fft port map(const_input,c1,xyz,c2,c_2);
fft port map(const_input,c2,xyz,c3,c_3);
and2 port map(c_1,c_2,temp);
or2 port map(c_3,temp,xyz);
end structure