vhdl code2.bak

来自「d flip flop t flip flop counter mux usin」· BAK 代码 · 共 14 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dec24d IS
PORT(A,B,EN_L:IN BIT;
Q0,Q1,Q2,Q3:OUT BIT);
END ENTITY;
ARCHITECTURE dataflow OF dec24d IS
BEGIN
Q0<=(NOT A)AND (NOT B) AND (NOT EN_L);
Q1<=( A)AND (NOT B) AND (NOT EN_L);
Q2<=(NOT A)AND (B) AND (NOT EN_L);
Q3<=(A)AND (B) AND (NOT EN_L);
END dataflow;