代码搜索：REF
找到约 10,000 项符合「REF」的源代码
代码结果 10,000
www.eeworm.com/read/451137/7470844
ref hdllib.ref
MO uart_top NULL uart_top.v vlg1A/uart__top.bin 1238638300
MO uart_rx NULL uart_rx.v vlg21/uart__rx.bin 1238646185
MO uart_tx NULL uart_tx.v vlg2B/uart__tx.bin 1238640924
MO baud_gen NULL baud_gen.
www.eeworm.com/read/448700/7526998
gif ref.gif
www.eeworm.com/read/448006/7541957
ref hdllib.ref
EN bcd_7seg NULL G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg.vhd sub00/vhpl00
EN bcd_7seg_sch NULL G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg_sch.vhf sub00/vhpl04
EN d3_8e_mxilinx_bcd_7seg_sch NULL G:/vijay_FPGA_L
www.eeworm.com/read/448006/7541958
ref hdpdeps.ref
V1 16
FL G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg.vhd 2006/02/22.15:48:16
EN work/BCD_7SEG FL G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg.vhd \
PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB iee
www.eeworm.com/read/448004/7542072
ref hdllib.ref
EN dvd100k NULL G:/GIRIJA/FPGApgms/bcd_cntr/dvd100k.vhd sub00/vhpl06
EN divd10 NULL F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/divd10.vhd sub00/vhpl02
EN bcd_cntr NULL G:/GIRIJA/FPGApgms/bcd_cntr/
www.eeworm.com/read/448004/7542073
ref hdpdeps.ref
V1 17
FL F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/testcnt.vhd 2005/06/07.19:19:24
EN work/TESTCNT FL F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/testcnt.vhd \
PB ieee/STD_LOGIC_1
www.eeworm.com/read/447999/7542225
ref hdllib.ref
EN dflipflop NULL G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd sub00/vhpl04
EN invtr NULL G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd sub00/vhpl06
EN dflip NULL G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd sub00/vhpl1
www.eeworm.com/read/447999/7542226
ref hdpdeps.ref
V1 33
FL G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd 2005/05/25.12:07:16
EN work/INVTR FL G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd \
PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_
www.eeworm.com/read/447996/7542365
ref hdllib.ref
EN dflipflop NULL G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd sub00/vhpl02
EN invtr NULL G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd sub00/vhpl04
EN dflip NULL G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd sub00/vhpl1
www.eeworm.com/read/447996/7542366
ref hdpdeps.ref
V1 32
FL G:/vijay_FPGA_LAB/alu_2bit/buff.vhd 2006/02/14.13:58:34
EN work/BUFF FL G:/vijay_FPGA_LAB/alu_2bit/buff.vhd \
PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LO