hdpdeps.ref

this program performs the functonality of 4 bit alu

V1 33
FL G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd 2005/05/25.12:07:16
EN work/INVTR           FL G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/INVTR/BEHAVIORAL FL G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd EN work/INVTR
FL G:/vijay_FPGA_LAB/4bit_alu/4bit_alu.vhd 2006/02/14.12:43:18
EN work/ALU_4BIT        FL G:/vijay_FPGA_LAB/4bit_alu/4bit_alu.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED \
      PH unisim/VCOMPONENTS
AR work/ALU_4BIT/BEHAVIORAL FL G:/vijay_FPGA_LAB/4bit_alu/4bit_alu.vhd \
      EN work/ALU_4BIT  CP TESTCNT        CP DFLIP          CP FBITADDR
FL G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd 2006/01/23.17:31:56
EN work/BUFF \
      FL G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/BUFF/BEHAVIORAL \
      FL G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd \
      EN work/BUFF
FL g:/vijay_fpga_lab/4bit_alu/4bit_alu.vhd 2006/01/23.10:27:10
FL G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd 2006/02/14.12:30:20
EN work/DFLIP           FL G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd \
      PB ieee/STD_LOGIC_1164 PH ieee/NUMERIC_STD
AR work/DFLIP/BEHAVIORAL FL G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd EN work/DFLIP \
      CP DFLIPFLOP      CP INVTR          CP BUFF
FL G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd 2005/05/25.12:08:36
EN work/FULLADDR        FL G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/FULLADDR/BEHAVIORAL FL G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd \
      EN work/FULLADDR
FL G:/vijay_FPGA_LAB/4bit_alu/buff.vhd 2005/08/05.10:27:54
FL G:/vijay_FPGA_LAB/4bit_alu/fbitaddr.vhd 2005/05/25.12:07:58
EN work/FBITADDR        FL G:/vijay_FPGA_LAB/4bit_alu/fbitaddr.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/FBITADDR/BEHAVIORAL FL G:/vijay_FPGA_LAB/4bit_alu/fbitaddr.vhd \
      EN work/FBITADDR  CP FULLADDR
FL G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd 2005/05/25.12:09:08
EN work/TESTCNT         FL G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/TESTCNT/BEHAVIORAL FL G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd \
      EN work/TESTCNT
FL G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd 2005/07/29.10:11:46
EN work/DFLIPFLOP       FL G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/DFLIPFLOP/BEHAVIORAL FL G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd \
      EN work/DFLIPFLOP