📄 hdllib.ref
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EN dflipflop NULL G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd sub00/vhpl02
EN invtr NULL G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd sub00/vhpl04
EN dflip NULL G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd sub00/vhpl10
AR buff behavioral G:/vijay_FPGA_LAB/alu_2bit/buff.vhd sub00/vhpl07
AR fulladdr behavioral G:/vijay_FPGA_LAB/alu_2bit/fulladder.vhd sub00/vhpl01
EN testcnt NULL G:/vijay_FPGA_LAB/alu_2bit/testcnt.vhd sub00/vhpl08
EN fulladdr NULL G:/vijay_FPGA_LAB/alu_2bit/fulladder.vhd sub00/vhpl00
AR fbitaddr behavioral G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd sub00/vhpl13
EN fbitaddr NULL G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd sub00/vhpl12
AR dflip behavioral G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd sub00/vhpl11
EN buff NULL G:/vijay_FPGA_LAB/alu_2bit/buff.vhd sub00/vhpl06
AR invtr behavioral G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd sub00/vhpl05
EN alu_2bit NULL G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd sub00/vhpl14
AR dflipflop behavioral G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd sub00/vhpl03
AR alu_2bit behavioral G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd sub00/vhpl15
AR testcnt behavioral G:/vijay_FPGA_LAB/alu_2bit/testcnt.vhd sub00/vhpl09
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