hdpdeps.ref

this program will give the functionality of bcd to seven segment display

V1 16
FL G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg.vhd 2006/02/22.15:48:16
EN work/BCD_7SEG        FL G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/BCD_7SEG/BEHAVIORAL FL G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg.vhd \
      EN work/BCD_7SEG
FL g:/girija/fpga/bcd_7seg/bcd_7seg.vhd 2005/04/25.13:21:34
FL G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg_sch.vhf 2006/03/09.14:52:28
EN work/D3_8E_MXILINX_BCD_7SEG_SCH FL G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg_sch.vhf \
      PB ieee/STD_LOGIC_1164 PH ieee/NUMERIC_STD
AR work/D3_8E_MXILINX_BCD_7SEG_SCH/BEHAVIORAL \
      FL G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg_sch.vhf \
      EN work/D3_8E_MXILINX_BCD_7SEG_SCH CP AND4 CP AND4B1  CP AND4B2         CP AND4B3
EN work/BCD_7SEG_SCH    FL G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg_sch.vhf \
      PB ieee/STD_LOGIC_1164 PH ieee/NUMERIC_STD
AR work/BCD_7SEG_SCH/BEHAVIORAL FL G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg_sch.vhf \
      EN work/BCD_7SEG_SCH CP BCD_7SEG    CP D3_8E_MXILINX_BCD_7SEG_SCH
FL G:/GIRIJA/FPGA/bcd_7seg/bcd_7seg.vhd 2005/05/30.12:34:30