hdllib.ref

this program performs the functonality of 4 bit alu

EN dflipflop NULL G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd sub00/vhpl04
EN invtr NULL G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd sub00/vhpl06
EN dflip NULL G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd sub00/vhpl12
EN alu_4bit NULL G:/vijay_FPGA_LAB/4bit_alu/4bit_alu.vhd sub00/vhpl00
AR buff behavioral G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd sub00/vhpl09
AR fulladdr behavioral G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd sub00/vhpl03
EN testcnt NULL G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd sub00/vhpl10
AR alu_4bit behavioral G:/vijay_FPGA_LAB/4bit_alu/4bit_alu.vhd sub00/vhpl01
EN fulladdr NULL G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd sub00/vhpl02
AR fbitaddr behavioral G:/vijay_FPGA_LAB/4bit_alu/fbitaddr.vhd sub00/vhpl15
EN fbitaddr NULL G:/vijay_FPGA_LAB/4bit_alu/fbitaddr.vhd sub00/vhpl14
AR dflip behavioral G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd sub00/vhpl13
EN buff NULL G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd sub00/vhpl08
AR invtr behavioral G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd sub00/vhpl07
AR dflipflop behavioral G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd sub00/vhpl05
AR testcnt behavioral G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd sub00/vhpl11