📄 hdllib.ref

📁 this program will give the functionality of bcd to seven segment display

💻 REF

字号:

EN bcd_7seg NULL G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg.vhd sub00/vhpl00
EN bcd_7seg_sch NULL G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg_sch.vhf sub00/vhpl04
EN d3_8e_mxilinx_bcd_7seg_sch NULL G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg_sch.vhf sub00/vhpl02
AR d3_8e_mxilinx_bcd_7seg_sch behavioral G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg_sch.vhf sub00/vhpl03
AR bcd_7seg behavioral G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg.vhd sub00/vhpl01

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