hdpdeps.ref

this program give the functionality bcd count

V1 17
FL F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/testcnt.vhd 2005/06/07.19:19:24
EN work/TESTCNT         FL F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/testcnt.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/TESTCNT/BEHAVIORAL \
      FL F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/testcnt.vhd EN work/TESTCNT
FL G:/GIRIJA/FPGA/bcd_cntr/bcd_cntr.vhd 2005/06/08.19:22:38
FL g:/girija/fpga/bcd_cntr/bcd_cntr.vhd 2005/06/07.10:48:08
FL G:/GIRIJA/FPGApgms/bcd_cntr/dvd100k.vhd 2005/06/09.11:15:24
EN work/DVD100K         FL G:/GIRIJA/FPGApgms/bcd_cntr/dvd100k.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/DVD100K/BEHAVIORAL FL G:/GIRIJA/FPGApgms/bcd_cntr/dvd100k.vhd \
      EN work/DVD100K
FL F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/divd10.vhd 2005/05/18.14:54:32
EN work/DIVD10          FL F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/divd10.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/DIVD10/BEHAVIORAL \
      FL F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/divd10.vhd EN work/DIVD10
FL G:/GIRIJA/FPGA/bcd_cntr/dvd100k.vhd 2005/06/09.11:15:24
FL G:/GIRIJA/FPGApgms/bcd_cntr/bcd_cntr.vhd 2005/06/09.12:55:02
EN work/BCD_CNTR        FL G:/GIRIJA/FPGApgms/bcd_cntr/bcd_cntr.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED \
      PH unisim/VCOMPONENTS
AR work/BCD_CNTR/BEHAVIORAL FL G:/GIRIJA/FPGApgms/bcd_cntr/bcd_cntr.vhd \
      EN work/BCD_CNTR  CP IBUF           CP DVD100K