hdpdeps.ref

this programs gives the functionality of 2bit alu

V1 32
FL G:/vijay_FPGA_LAB/alu_2bit/buff.vhd 2006/02/14.13:58:34
EN work/BUFF            FL G:/vijay_FPGA_LAB/alu_2bit/buff.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/BUFF/BEHAVIORAL FL G:/vijay_FPGA_LAB/alu_2bit/buff.vhd EN work/BUFF
FL G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd 2005/05/25.12:07:16
EN work/INVTR           FL G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/INVTR/BEHAVIORAL FL G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd EN work/INVTR
FL G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd 2005/07/29.10:11:46
EN work/DFLIPFLOP       FL G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/DFLIPFLOP/BEHAVIORAL FL G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd \
      EN work/DFLIPFLOP
FL G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd 2006/02/24.16:09:40
EN work/ALU_2BIT        FL G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED \
      PH unisim/VCOMPONENTS
AR work/ALU_2BIT/BEHAVIORAL FL G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd \
      EN work/ALU_2BIT  CP TESTCNT        CP DFLIP          CP FBITADDR
FL G:/vijay_FPGA_LAB/alu_2bit/testcnt.vhd 2006/02/22.15:46:46
EN work/TESTCNT         FL G:/vijay_FPGA_LAB/alu_2bit/testcnt.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/TESTCNT/BEHAVIORAL FL G:/vijay_FPGA_LAB/alu_2bit/testcnt.vhd \
      EN work/TESTCNT
FL G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd 2006/02/14.13:58:38
EN work/DFLIP           FL G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd \
      PB ieee/STD_LOGIC_1164 PH ieee/NUMERIC_STD
AR work/DFLIP/BEHAVIORAL FL G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd EN work/DFLIP \
      CP DFLIPFLOP      CP INVTR          CP BUFF
FL g:/vijay_fpga_lab/alu_2bit/alu_2bit.vhd 2006/02/18.09:23:18
FL G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd 2006/02/14.14:02:28
EN work/FBITADDR        FL G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/FBITADDR/BEHAVIORAL FL G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd \
      EN work/FBITADDR  CP FULLADDR
FL G:/vijay_FPGA_LAB/alu_2bit/fulladder.vhd 2006/02/22.15:46:46
EN work/FULLADDR        FL G:/vijay_FPGA_LAB/alu_2bit/fulladder.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/FULLADDR/BEHAVIORAL FL G:/vijay_FPGA_LAB/alu_2bit/fulladder.vhd \
      EN work/FULLADDR