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找到约 10,000 项符合
Logic Analyzer 的代码
v9_3.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity Adder is
port(ManA : in std_logic_vector(24 downto 0);
ManB : in std_logic_vector(24 downto
v9_2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity Flt2Fix is
port(DInA : in std_logic_vector(31 downto 0);
DInB : in std_logic_vector(31 downto 0
v9_4.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Fix2Flt is
port(AddO : in std_logic_vector(24 downto 0);
DOut : out std_logic_vector(31 do
v9_5.vhd
library ieee;
use ieee.std_logic_1164.all;
entity FltAdder is
port(DInA : in std_logic_vector(31 downto 0);
DInB : in std_logic_vector(31 downto 0);
DOut : out std_logic_vect
v8_11.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
entity V8_11 is
port(addr : IN std_logic
v5_1.vhd
library ieee;
use ieee.std_logic_1164.all;
entity V5_1 is
port(Sel : in std_logic_vector(1 downto 0);
OutD : out std_logic_vector(1 downto 0));
end V5_1;
architecture a of V5_1
v5_0.vhd
library ieee;
use ieee.std_logic_1164.all;
entity V5_0 is
port(addr : in std_logic_vector(5 downto 0);
rw : in std_logic;
a4rd : out std_logic);
end V5_0;
architectur
v10_10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity Flt2Fix is
port(DInA : in std_logic_vector(31 downto 0);
DInB : in std_logic_vector(31 downto 0
v10_13.vhd
library ieee;
use ieee.std_logic_1164.all;
entity FltAdder is
port(DInA : in std_logic_vector(31 downto 0);
DInB : in std_logic_vector(31 downto 0);
DOut : out std_logic_vect
v10_11.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity Adder is
port(ManA : in std_logic_vector(24 downto 0);
ManB : in std_logic_vector(24 downto