v10_10.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity Flt2Fix is
    port(DInA  : in  std_logic_vector(31 downto 0);
         DInB  : in  std_logic_vector(31 downto 0);
         ManA  : out std_logic_vector(24 downto 0);
         ManB  : out std_logic_vector(24 downto 0);
         Exp   : out std_logic_vector(7 downto 0);
         Clk   : in  std_logic);
end Flt2Fix;

architecture A_Flt2Fix of Flt2Fix is
	signal ManInA  : std_logic_vector(22 downto 0);
	signal ManInB  : std_logic_vector(22 downto 0);
	signal ManInAi : std_logic_vector(24 downto 0);
	signal ManInBi : std_logic_vector(24 downto 0);
	signal ExpInA  : std_logic_vector(7 downto 0);
	signal ExpInB  : std_logic_vector(7 downto 0);
	signal Diff    : std_logic_vector(7 downto 0);
	signal SignA   : std_logic;
	signal SignB   : std_logic;
begin

    process(Clk)
    begin
        if Clk = '1' and Clk'event then
            ManInA <= DInA(22 downto 0);
            ManInB <= DInB(22 downto 0);
            ExpInA <= DInA(30 downto 23);
            ExpInB <= DInB(30 downto 23);
            SignA <= DInA(31);
            SignB <= DInB(31);
        end if;
    end process;
    
    process(ExpInA,ExpInB,Diff,ManInAi,ManInBi)
    begin
        if (ExpInA > ExpInB) then --modified here
        	Diff <= ExpInA - ExpInB;
        	ManA <= ManInAi;
        	ManB <= SHR(ManInBi,Diff);
        	Exp  <= ExpInA;
        else 
        	Diff <= ExpInB - ExpInA;
        	ManB <= ManInBi;
        	ManA <= SHR(ManInAi,Diff);
        	Exp  <= ExpInB;
        end if;        
    end process;
    
    ManInAi <= "01" & ManInA when SignA = '0' else
               not("01" & ManInA) + 1;
    ManInBi <= "01" & ManInB when SignB = '0' else
               not("01" & ManInB) + 1;
    
end A_Flt2Fix;