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Logic Analyzer 的代码
portx.vhd
--**********************************************************************************************
-- Parallel Port Peripheral for the AVR Core
-- Version 0.3 02.11.2002
-- Designed by Ruslan Lep
system.vhd
-- ------------------------------------------------
-- Model : Top - Level System Component
--
-- Author : Michael Mayer,
-- Department of Electrical Engineering
--
vga.vhd
-------------------------------------------------------------------------------
-- vga.vhd
--
-- Author(s): Ashley Partis and Jorgen Peddersen
-- Created: Jan 2001
-- Last Modified: Jan
headers.vhi
-- VHDL Instantiation Created from source file headers.vhd -- 16:19:09 03/20/2004
--
-- Notes:
-- 1) This instantiation template has been automatically generated using types
-- std_logic and st
register2.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity register2 is
Port (clk, reset: in std_logic;
cop: in std_logic_vector
mux6.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux6 is
Generic ( size : integer := 8 );
Port ( d0 : in std_logic_vector(
vgamem.vhi
-- VHDL Instantiation Created from source file vgamem.vhd -- 16:22:49 03/20/2004
--
-- Notes:
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std
giftest.vhd
-- VHDL Test Bench Created from source file gif.vhd -- 15:30:39 03/22/2004
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the
lzw.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lzw is
Port ( start,resetin, clk : in std_logic;
addr : out std_
xianshi.vhd
--利用列扫描信号显示数码管
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xianshi is
port(
clk : in std_logic;
sel : in std_logic_vector(2 downto 0);
ledms1: out