portx.vhd

another avr core porocesssor vhdl source code

--**********************************************************************************************
--  Parallel Port Peripheral for the AVR Core
--  Version 0.3 02.11.2002	
--  Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;

use WORK.AVRuCPackage.all;

entity pport is 
	generic(
	        PORTX_Adr : std_logic_vector(IOAdrWidth-1 downto 0);
	        DDRX_Adr  : std_logic_vector(IOAdrWidth-1 downto 0);
			PINX_Adr  : std_logic_vector(IOAdrWidth-1 downto 0)
			);
	port(
	                   -- AVR Control
               ireset     : in std_logic;
               cp2	      : in std_logic;
               adr        : in std_logic_vector(5 downto 0);
               dbus_in    : in std_logic_vector(7 downto 0);
               dbus_out   : out std_logic_vector(7 downto 0);
               iore       : in std_logic;
               iowe       : in std_logic;
               out_en     : out std_logic; 
			            -- External connection
			   pinx       : inout std_logic_vector(7 downto 0));
end pport;

architecture rtl of pport is
signal PORTX_Int : std_logic_vector(7 downto 0) := (others => '0');
signal DDRX  : std_logic_vector(7 downto 0) := (others => '0');

signal PORTX_Wr_En : std_logic := '0';
signal DDRX_Wr_En  : std_logic := '0';

signal PORTX_Rd : std_logic := '0';
signal DDRX_Rd  : std_logic := '0';
signal PINX_Rd  : std_logic := '0';

begin

PORTX_Wr_En <= '1' when (adr=PORTX_Adr and iowe='1')else '0';
DDRX_Wr_En  <= '1' when (adr=DDRX_Adr and iowe='1')else '0';

PORTX_Rd <= '1' when (adr=PORTX_Adr and iore='1')else '0';
DDRX_Rd  <= '1' when (adr=DDRX_Adr and iore='1')else '0';	
PINX_Rd  <= '1' when (adr=PINX_Adr and iore='1')else '0';	

out_en <= PORTX_Rd or DDRX_Rd or PINX_Rd;
	
PORTX_DFF:process(cp2,ireset)
begin
if (ireset='0') then                  -- Reset
 PORTX_Int <= (others => '0'); 
  elsif (cp2='1' and cp2'event) then  -- Clock
  if PORTX_Wr_En='1' then             -- Clock enable
  PORTX_Int <= dbus_in;
  end if;
  end if;
end process;		

DDRX_DFF:process(cp2,ireset)
begin
if (ireset='0') then                  -- Reset
 DDRX <= (others => '0'); 
  elsif (cp2='1' and cp2'event) then  -- Clock
  if DDRX_Wr_En='1' then              -- Clock enable
  DDRX <= dbus_in;
  end if;
  end if;
end process;		

Output_Buffers:for i in pinx'range generate
pinx(i) <= PORTX_Int(i) when DDRX(i)='1' else 'Z';
dbus_out(i) <= (PORTX_Int(i) and PORTX_Rd)or(DDRX(i) and DDRX_Rd)or(pinx(i) and PINX_Rd);
end generate;	

end rtl;