register2.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity register2 is
    Port (clk, reset: in std_logic;
	 			cop: in std_logic_vector (1 downto 0);
				indata: in std_logic;
				shift: in std_logic_vector (11 downto 0);
				outdata: out std_logic_vector (11 downto 0)
			 );
end register2;

architecture Behavioral of register2 is
signal regout : std_logic_vector(11 downto 0);
signal offset : std_logic_vector(1 downto 0);

begin


process (clk)
variable data: std_logic_vector (11 downto 0);
variable bitdata: std_logic;
begin

bitdata := indata;

if (clk'EVENT and clk='1') THEN
    
    if (reset = '1') THEN data := "000000000000"; end if;
	if (cop = "01") THEN  data(10 downto 0) := data(11 downto 1); data(11) := bitdata; 
    elsif (cop = "00") THEN data := data; end if;
end if;

regout <= data;
end process;


process (shift, regout)
	variable move : integer;
begin
move := conv_integer(shift);

if (move < 512) then offset <= "11";
elsif (move < 1024) then offset <= "10";
elsif (move < 2048) then offset <= "01";
elsif (move < 4096) then offset <= "00"; 
end if;
end process;


outdata <= regout when offset = "00" else
				 "0" & regout(11 downto 1) when offset = "01" else
				 "00" & regout(11 downto 2) when offset = "10" else
				 "000" & regout(11 downto 3);

end Behavioral;