📄 vgamem.vhi
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-- VHDL Instantiation Created from source file vgamem.vhd -- 16:22:49 03/20/2004
--
-- Notes:
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
COMPONENT vgamem
PORT(
reset : IN std_logic;
clock : IN std_logic;
imwidth : IN std_logic_vector(9 downto 0);
imheight : IN std_logic_vector(9 downto 0);
hsyncb : OUT std_logic;
vsyncb : OUT std_logic;
addr : OUT std_logic_vector(19 downto 0);
oeb : OUT std_logic;
web : OUT std_logic;
pixelclk : OUT std_logic;
pblank : OUT std_logic
);
END COMPONENT;
Inst_vgamem: vgamem PORT MAP(
reset => ,
clock => ,
hsyncb => ,
vsyncb => ,
addr => ,
oeb => ,
web => ,
pixelclk => ,
pblank => ,
imwidth => ,
imheight =>
);
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