📄 headers.vhi
字号:
-- VHDL Instantiation Created from source file headers.vhd -- 16:19:09 03/20/2004
--
-- Notes:
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
COMPONENT headers
PORT(
clk : IN std_logic;
rstL : IN std_logic;
start : IN std_logic;
paletteProgDone : IN std_logic;
readData : IN std_logic_vector(15 downto 0);
addr : OUT std_logic_vector(19 downto 0);
writeData : OUT std_logic_vector(15 downto 0);
oen : OUT std_logic;
wen : OUT std_logic;
height : OUT std_logic_vector(9 downto 0);
width : OUT std_logic_vector(9 downto 0);
codesize : OUT std_logic_vector(3 downto 0);
coltablecode : OUT std_logic_vector(2 downto 0);
startPaletteProg : OUT std_logic;
done : OUT std_logic
);
END COMPONENT;
Inst_headers: headers PORT MAP(
clk => ,
rstL => ,
start => ,
paletteProgDone => ,
readData => ,
addr => ,
writeData => ,
oen => ,
wen => ,
height => ,
width => ,
codesize => ,
coltablecode => ,
startPaletteProg => ,
done =>
);
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -