giftest.vhd

vhdl code for GIF Image Viewer

-- VHDL Test Bench Created from source file gif.vhd -- 15:30:39 03/22/2004
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	COMPONENT gif
	PORT(
		clk : IN std_logic;
		resetL : IN std_logic;
		start : IN std_logic;    
		ldata : INOUT std_logic_vector(15 downto 0);
		rdata : INOUT std_logic_vector(15 downto 0);
		ramdacdata : INOUT std_logic_vector(7 downto 0);
		rs : INOUT std_logic_vector(2 downto 0);      
		lcen : OUT std_logic;
		rcen : OUT std_logic;
		loen : OUT std_logic;
		roen : OUT std_logic;
		lwen : OUT std_logic;
		rwen : OUT std_logic;
		laddr : OUT std_logic_vector(18 downto 0);
		raddr : OUT std_logic_vector(18 downto 0);
		rdN : OUT std_logic;
		wrN : OUT std_logic;
		pixelclk : OUT std_logic;
		hsyncb : OUT std_logic;
		vsyncb : OUT std_logic;
		pblank : OUT std_logic;
		triste : OUT std_logic
		);
	END COMPONENT;
	component sram is
	    Generic (
		 		mem_words : integer := 524287;
				word_size : integer := 16;
	
				tAA : time := 15 ns;
				tACE : time := 15 ns;
				tOE : time := 7 ns;
				tOH : time := 3 ns;
				tCLZ : time := 1 ns;
				tCHZ : time := 7 ns;
				tOLZ : time := 1 ns;
				tOHZ : time := 7 ns;
	
				tCW : time := 10 ns;
				tAW : time := 10 ns;
				tAS : time := 0 ns;
				tWP1 : time := 10 ns;
				tWP2 : time := 15 ns;
				tAH : time := 0 ns;		-- unimplemented
				tWR : time := 0 ns;		-- unimplemented
				tDW : time := 7 ns;
				tDH : time := 0 ns;		-- unimplemented
				tWZ : time := 7 ns;
				tOW : time := 3 ns
		 );
	    Port ( addr : in std_logic_vector(18 downto 0);
	           ceN : in std_logic;
	           oeN : in std_logic;
	           weN : in std_logic;
				  load : in std_logic;
				  filename : in string(1 to 12);
				  load_addr : in natural;
	           data : inout std_logic_vector(15 downto 0);
				  violation : out std_logic
				  );
	end component;

	SIGNAL clk :  std_logic;
	SIGNAL resetL :  std_logic;
	SIGNAL start :  std_logic;
	SIGNAL ldata :  std_logic_vector(15 downto 0);
	SIGNAL rdata :  std_logic_vector(15 downto 0);
	SIGNAL lcen :  std_logic;
	SIGNAL rcen :  std_logic;
	SIGNAL loen :  std_logic;
	SIGNAL roen :  std_logic;
	SIGNAL lwen :  std_logic;
	SIGNAL rwen :  std_logic;
	SIGNAL laddr :  std_logic_vector(18 downto 0);
	SIGNAL raddr :  std_logic_vector(18 downto 0);
	SIGNAL ramdacdata :  std_logic_vector(7 downto 0);
	SIGNAL rdN :  std_logic;
	SIGNAL wrN :  std_logic;
	SIGNAL rs :  std_logic_vector(2 downto 0);
	SIGNAL pixelclk :  std_logic;
	SIGNAL hsyncb :  std_logic;
	SIGNAL vsyncb :  std_logic;
	SIGNAL pblank :  std_logic;
	SIGNAL triste :  std_logic;

	signal filenameleft, filenameright : string(1 to 12);
	signal loadleftaddr, loadrightaddr : natural;
    signal loadleft, loadright, violationleft, violationright : std_logic;

BEGIN

	uut: gif PORT MAP(
		clk => clk,
		resetL => resetL,
		start => start,
		ldata => ldata,
		rdata => rdata,
		lcen => lcen,
		rcen => rcen,
		loen => loen,
		roen => roen,
		lwen => lwen,
		rwen => rwen,
		laddr => laddr,
		raddr => raddr,
		ramdacdata => ramdacdata,
		rdN => rdN,
		wrN => wrN,
		rs => rs,
		pixelclk => pixelclk,
		hsyncb => hsyncb,
		vsyncb => vsyncb,
		pblank => pblank,
		triste => triste
	);

    lram : sram PORT MAP(
   		addr => laddr,
		oen => loen,
		wen => lwen,
		cen => lcen,
		data => ldata,
		load => loadleft,
		load_addr => loadleftaddr,
		filename => filenameleft,
		violation => violationleft);
	rram : sram
	port map (
		addr => raddr,
		oen => roen,
		wen => rwen,
		cen => rcen,
		data => rdata,
		load => loadright,
		load_addr => loadrightaddr,
		filename => filenameright,
		violation => violationright);



-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN

      resetL <= '0';
      start <= '0';

      wait for 10 ns;
	loadleft <= '0';
	loadright <= '0';
	loadleftaddr <= 0;
	loadrightaddr <= 0;
	filenameleft <= "            ";
	filenameright <= "gifdata1.hex";

	loadright <= '1';
	wait for 10 ns;
	loadright <= '0';


      wait for 200 ns;
      resetL <= '1';
      wait for 200 ns;
      start <= '1';
      wait for 20 ns;
      start <= '0';

      wait; -- will wait forever
   END PROCESS;

   process
   begin
       clk <= '0';
       loop
            wait for 10 ns;
            clk <= not clk;
       end loop;
   end process;
-- *** End Test Bench - User Defined Section ***

END;