📄 mux6.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux6 is
Generic ( size : integer := 8 );
Port ( d0 : in std_logic_vector(size-1 downto 0);
d1 : in std_logic_vector(size-1 downto 0);
d2 : in std_logic_vector(size-1 downto 0);
d3 : in std_logic_vector(size-1 downto 0);
d4 : in std_logic_vector(size-1 downto 0);
d5 : in std_logic_vector(size-1 downto 0);
s : in std_logic_vector(2 downto 0);
o : out std_logic_vector(size-1 downto 0));
end mux6;
architecture Behavioral of mux6 is
begin
with s select o <=
d0 when "000",
d1 when "001",
d2 when "010",
d3 when "011",
d4 when "100",
d5 when others;
end Behavioral;
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