📄 lzw.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lzw is
Port ( start,resetin, clk : in std_logic;
addr : out std_logic_vector(19 downto 0);
rddata : in std_logic_vector(15 downto 0);
wrdata : out std_logic_vector(15 downto 0);
wen : out std_logic;
oen, done1: out std_logic);
end lzw;
architecture structural of lzw is
COMPONENT counter
generic ( size : integer := 16);
PORT(
cop : IN std_logic_vector(1 downto 0);
reset : IN std_logic;
clk : IN std_logic;
outdata : OUT std_logic_vector(size-1 downto 0)
);
END COMPONENT;
COMPONENT counter2
generic ( size : integer := 16);
PORT(
cop : IN std_logic_vector(1 downto 0);
reset : IN std_logic;
clk : IN std_logic;
indata : IN std_logic_vector(size-1 downto 0);
outdata : OUT std_logic_vector(size-1 downto 0)
);
END COMPONENT;
COMPONENT counter3
generic ( size : integer := 16);
PORT(
cop : IN std_logic_vector(1 downto 0);
reset : IN std_logic;
clk : IN std_logic;
outdata : OUT std_logic_vector(size-1 downto 0)
);
END COMPONENT;
COMPONENT reg
Generic ( size : integer := 8 );
PORT(
d : IN std_logic_vector(size-1 downto 0);
rstL : IN std_logic;
clk : IN std_logic;
ce : IN std_logic;
q : OUT std_logic_vector(size-1 downto 0)
);
END COMPONENT;
COMPONENT register1
PORT(
clk : IN std_logic;
reset : IN std_logic;
cop : IN std_logic_vector(1 downto 0);
indata : IN std_logic_vector(7 downto 0);
outdata : OUT std_logic;
temp: OUT std_logic_vector (7 downto 0)
);
END COMPONENT;
COMPONENT register2
PORT(
clk : IN std_logic;
reset : IN std_logic;
cop : IN std_logic_vector(1 downto 0);
indata : IN std_logic;
shift : IN std_logic_vector(11 downto 0);
outdata : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT mux5
Generic ( size : integer := 8 );
Port ( d0 : in std_logic_vector(size-1 downto 0);
d1 : in std_logic_vector(size-1 downto 0);
d2 : in std_logic_vector(size-1 downto 0);
d3 : in std_logic_vector(size-1 downto 0);
d4 : in std_logic_vector(size-1 downto 0);
s : in std_logic_vector(2 downto 0);
o : out std_logic_vector(size-1 downto 0));
END COMPONENT;
COMPONENT mux6
Generic (size : integer := 8 );
PORT(
d0 : IN std_logic_vector(size-1 downto 0);
d1 : IN std_logic_vector(size-1 downto 0);
d2 : IN std_logic_vector(size-1 downto 0);
d3 : IN std_logic_vector(size-1 downto 0);
d4 : IN std_logic_vector(size-1 downto 0);
d5 : IN std_logic_vector(size-1 downto 0);
s : IN std_logic_vector(2 downto 0);
o : OUT std_logic_vector(size-1 downto 0)
);
END COMPONENT;
TYPE stateT IS (ready, state0, state0_1, state1, state1_1, state1_2, state2, state3, state4, state4_1, state5, state5_0_0, state5_0_1, state5_0_2,
state5_1, state5_2, state6, state6_1, state6_2, state7_1, state7_2, state7_3, state4_5, state4_0_0,
state7, state8, state9, state9_1, state9_2, state10, state11, state12, state13, state14,
state15, state16, state17, state10_1, state11_1, state11_2, state13_1, state13_2, state13_3,
state14_1, state15_1, state1_1_1, state1_1_2, ready2, ready3, state4_2, state4_3,
state13_1_1, state15_1_1, state13_2_1, state27, state27_1, state27_2, state27_3, state7_0, state6_0, done);
SIGNAL Cop1, Cop2, Cop3, Cop4, Cop5, Cop6, opin1, opin2: std_logic_vector (1 downto 0);
SIGNAL inputaddr, outputaddr, phaseaddr, phaseaddr1, bottomaddr, stackaddr, stringpointerplus, stringpointer2, stringword2, stringword3, readydata2, storedpointer2, storedpointer3: std_logic_vector (19 downto 0);
SIGNAL phase, stacksize, readydata: std_logic_vector (11 downto 0);
SIGNAL bottomaddr2: std_logic_vector (12 downto 0);
SIGNAL stackaddr2: std_logic_vector (13 downto 0);
SIGNAL seladdr, seladdr2, select1: std_logic_vector (2 downto 0);
SIGNAL memfetch, codesize, codesizefix: std_logic_vector (3 downto 0);
SIGNAL datain, reset, reset2, reset3, reset4, reset6, opout1, opout2, opout3, opoutstring, opinstring: std_logic;
SIGNAL tempdata: std_logic_vector (7 downto 0);
SIGNAL pendwrdata1, pendwrdata2, readydata11, stringpointer, stringword, storedpointer: std_logic_vector (15 downto 0);
SIGNAL resetL: std_logic;
SIGNAL state: stateT;
begin
resetL <= not reset;
inputaddr_Counter: counter2
GENERIC MAP (size => 20)
PORT MAP (clk => clk, cop => Cop6, reset => reset6, outdata => inputaddr, indata => x"03000");
outputaddr_Counter: counter2
GENERIC MAP (size => 20)
PORT MAP (clk => clk, cop => Cop1, reset => reset, outdata => outputaddr, indata => x"80000");
phrase_Counter: counter2
GENERIC MAP (size => 12)
PORT MAP (clk => clk, cop => cop2, reset => reset, outdata => phase, indata => x"101");
stacksize_Counter: counter3
GENERIC MAP (size => 12)
PORT MAP (clk => clk, cop => cop3, reset => reset, outdata => stacksize);
memfetch_Counter: counter
GENERIC MAP (size => 4)
PORT MAP (clk => clk, cop => cop4, reset => reset2, outdata => memfetch);
codesize_Counter: counter
GENERIC MAP (size => 4)
PORT MAP (clk => clk, cop => cop5, reset => reset3, outdata => codesize);
reg1: register1 PORT MAP(clk => clk, cop => opin1, reset => reset4, indata => rddata(7 downto 0), outdata => datain, temp => tempdata);
reg2: register2 PORT MAP(clk => clk, cop => opin2, reset => reset4, indata => datain, outdata => readydata, shift => phase);
reg3: reg GENERIC MAP (size => 16) PORT MAP(clk => clk, ce => opout1, rstL => resetL, d => readydata11, q => pendwrdata1);
reg7: reg GENERIC MAP (size => 16) PORT MAP(clk => clk, ce => opout3, rstL => resetL, d => stringpointer, q => storedpointer);
reg4: reg GENERIC MAP (size => 16) PORT MAP(clk => clk, ce => opout2, rstL => resetL, d=> rddata, q => pendwrdata2);
reg5: reg GENERIC MAP (size => 16) PORT MAP(clk => clk, ce => opoutstring, rstL => resetL, d=> rddata, q => stringpointer);
reg6: reg GENERIC MAP (size => 16) PORT MAP(clk => clk, ce => opinstring, rstL => resetL, d=> rddata, q => stringword);
mux1: mux5 GENERIC MAP (size => 16) PORT MAP (d0 => readydata11, d1 => pendwrdata2, d2 => stringpointer, d3 => stringword, d4 => "0000000000000000", s => select1, o => wrdata);
addrmux: mux6 GENERIC MAP (size => 20) PORT MAP (d0 => phaseaddr, d1 => inputaddr, d2=> outputaddr, d3 => stringpointer2, d4 => stringword2, d5 => stringword3, s => seladdr, o => addr);
phaseaddrmux: mux6 GENERIC MAP (size => 20) PORT MAP (d0 => phaseaddr1, d1 => bottomaddr, d2 => stackaddr, d3 => readydata2, d4 => stringpointerplus, d5 => storedpointer3, s => seladdr2, o => phaseaddr);
bottomaddr2 <= "0"&phase;
stackaddr2 <= "00"&stacksize;
bottomaddr <= "0000000"&(bottomaddr2+4096);
stackaddr <= "000000"&(8192+stackaddr2);
readydata2 <= "00000000"&(readydata + 1);
stringpointerplus <= (4096 + readydata2);
stringpointer2 <= "0000"&stringpointer;
stringword2 <= "0000"&stringword;
phaseaddr1 <= "00000000"&phase;
readydata11 <= "0000"&readydata;
stringword3 <= (stringword2 + 4096);
storedpointer2 <= "0000"&storedpointer;
storedpointer3 <= (storedpointer2 + 4096);
PROCESS(clk, resetin)
BEGIN
IF (resetin = '1') THEN state <= ready;
ELSIF (clk'EVENT AND clk = '1') THEN
wen <= '1';
oen <= '0';
reset <= '0';
reset2 <= '0';
reset3 <= '0';
reset4 <= '0';
reset6 <= '0';
Cop1 <= "00";
Cop2 <= "00";
Cop3 <= "00";
Cop4 <= "00";
Cop5 <= "00";
Cop6 <= "00";
Opin1 <= "00";
Opin2 <= "00";
select1 <= "000";
opout1 <= '0';
opout2 <= '0';
opout3 <= '0';
opoutstring <= '0';
opinstring <= '0';
seladdr2 <= "000";
seladdr <= "000";
CASE state IS
WHEN ready => IF (start = '1') THEN state <= ready2; ELSE state <= ready; reset <= '1'; reset2 <= '1'; reset6 <= '1'; END IF;
WHEN ready2 => state <= ready3; seladdr <= "001"; opin1 <= "01"; Cop6 <= "11";
WHEN ready3 => state <= state0; Cop6 <= "01";
WHEN state0 => state <= state0_1; cop2 <= "11"; codesizefix <= "1001"; reset <= '1'; --get all data ready
WHEN state0_1=> reset3 <= '1'; state <= state1; cop2 <= "01";
WHEN state1_1_1 => cop4 <= "01";
opin1 <= "10";
opin2 <= "01";
state <= state1_1_2;
WHEN state1 => IF (memfetch = "1000") THEN state <= state1_1; --keep scootching data until memfetch = 0 or codesize = 0
ELSE state <= state1_1_1;END IF;
WHEN state1_1_2 => IF (codesize = codesizefix-1) THEN state <= state2; ELSE cop5 <= "01"; state <= state1; END IF;
WHEN state1_1 => state <= state1_2; seladdr <= "001"; opin1 <= "01"; --use inputaddr to fetch data
WHEN state1_2 => state <= state1_1_1; reset2 <= '1'; cop6 <= "01"; --reset memfetch counter and load data from input memory
WHEN state2 => IF (phase >= 256) THEN codesizefix <= "1001"; --check readydata to determine action and fix codesize
ELSIF (phase >= 512) THEN codesizefix <= "1010";
ELSIF (phase >= 1024) THEN codesizefix <= "1011";
ELSIF (phase >= 2048) THEN codesizefix <= "1100";
END IF;
IF (readydata < 256) THEN state <= state3;
ELSIF (readydata = 256) THEN state <= state0;
ELSIF (readydata = 257) THEN state <= done;
ELSIF (readydata > 257) THEN state <= state5_0_0; END IF;
WHEN state3 => state <= state4; --case < 256, load readydata to register.
WHEN state4 => state <= state4_0_0; seladdr2 <= "001"; seladdr <= "000"; wen <= '0'; select1 <= "000"; --case < 256, write to string table
WHEN state4_0_0 => state <= state4_3;
WHEN state4_3=> state <= state4_1; select1 <= "000"; seladdr <= "010"; wen <= '0';
WHEN state4_1=> state <= state4_2; --case <256, write to output memory
WHEN state4_2=> state <= state4_5; select1 <= "100"; seladdr2 <= "000"; seladdr <= "000"; wen <= '0';
WHEN state4_5=> state <= state0_1; Cop1 <= "01";
WHEN state5_0_0 => IF (phase - 1 = readydata) THEN state <= state5_0_1; ELSE state <= state5; END IF;
WHEN state5_0_1 => state <= state5_0_2; select1 <= "000"; seladdr2 <= "000"; seladdr <= "000"; wen <= '0'; --special case, write phase-1 at phase pointer section.
WHEN state5_0_2 => state <= state5;
WHEN state5 => state <= state5_1; seladdr2 <= "011"; seladdr <= "000"; opoutstring <= '1'; --case >257, read readydata+1
WHEN state5_1 => state <= state5_2; --case >257, store in reg5 -> stringpointer
WHEN state5_2 => IF (stringpointer = 0) THEN state <= state27; ELSE state <= state6_0; END IF; --case >257, compare to zero
WHEN state27 => state <= state27_1; seladdr2 <= "100"; seladdr <= "000"; Opout2 <= '1'; --case pointer = 0 off the bat, get readydata + 1 + 4096 and store at pendwrdata2
WHEN state27_1 => state <= state27_2;
WHEN state27_2 => state <= state27_3; seladdr2 <= "001"; seladdr <= "000"; wen <= '0'; select1 <= "001"; --write it back to memory location phase + 4096
WHEN state27_3 => state <= state8;
WHEN state6_0 => state <= state6; opout3 <= '1';
WHEN state6 => state <= state6_1; seladdr <= "011"; opoutstring <= '1'; --case >257, use stringpointer as address
WHEN state6_1 => state <= state6_2; --case >257, store new pointer to reg5 -> stringpointer
WHEN state6_2 => IF (stringpointer = 0) THEN state <= state7_0; ELSE state <= state6_0; END IF; --case >257, compare to zero
WHEN state7_0 => state <= state7;
WHEN state7 => state <= state7_1; seladdr2 <= "101"; seladdr <= "000"; Opout2 <= '1'; --case >257, get stringpointer + 4096 for character
WHEN state7_1 => state <= state7_2; --case >257, store at register 4 as phase+1 single character
WHEN state7_2 => state <= state7_3; seladdr2 <= "001"; seladdr <= "000"; wen <= '0'; select1 <= "001"; -- store end of linklist to character section of phase+4096
WHEN state7_3 => state <= state8;
WHEN state8 => state <= state9; seladdr2 <= "000"; seladdr <= "000"; select1 <= "000"; wen <= '0'; -- store 257+ value to pointer section of phase
WHEN state9 => seladdr2 <= "000"; seladdr <= "000"; state <= state9_1; opoutstring <= '1'; --load current phase pointer
WHEN state9_1 => state <= state9_2; --store at reg5 as stringpointer
WHEN state9_2 => IF (stringpointer = 0) THEN state <= state12; ELSE state <= state10; END IF; --compare to zero
WHEN state10 => seladdr2 <= "010"; seladdr <= "000"; wen <= '0'; select1 <= "010"; state <= state10_1; --if not zero push current stringpointer
WHEN state10_1 => Cop3 <= "01"; state <= state11; --increase stacksize
WHEN state11 => seladdr <= "011"; state <= state11_1; opoutstring <= '1'; --use stringpointer to continue dig
WHEN state11_1 => state <= state11_2; --store next pointer as current stringpointer
WHEN state11_2 => IF (stringpointer = 0) THEN state <= state12; ELSE state <= state10; END IF; --compare again
WHEN state12 => IF (stacksize > 0) THEN state <= state13; ELSE state <= state15; END IF; --compare stacksize
WHEN state13 => Cop3 <= "10"; state <= state13_1; --pop stack
WHEN state13_1 => state <= state13_1_1; seladdr2 <= "010"; seladdr <= "000"; opinstring <= '1'; --store at current stringpointer
WHEN state13_1_1 => state <= state13_2;
WHEN state13_2 => seladdr <= "101"; state <= state13_2_1; opinstring <= '1'; --use that as address to get character
WHEN state13_2_1 => state <= state13_3;
WHEN state13_3 => state <= state14; --store at reg6 as stringword
WHEN state14 => select1 <= "011"; wen <= '0'; seladdr <= "010"; state <= state14_1; --store stringdata to output memory
WHEN state14_1 => Cop1 <= "01"; IF (stacksize > 0) THEN state <= state13; ELSE state <= state15; END IF; --check stacksize again
WHEN state15 => seladdr2 <= "001"; seladdr <= "000"; state <= state15_1; opinstring <= '1'; --get character stored at bottom of current phase
WHEN state15_1 => state <= state15_1_1; --store as current stringdata at reg6
WHEN state15_1_1 => state <= state16;
WHEN state16 => select1 <= "011"; wen <= '0'; seladdr <= "010"; state <= state17; --store to the output
WHEN state17 => state <= state0_1; cop1 <= "01"; --go back to state0_1
WHEN done => done1 <= '1'; state <= ready;
END CASE;
END IF;
END PROCESS;
END structural;
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