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Logic Analyzer 的代码
flash.vhd
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--*************************************************************************************************
i2cbasics_package.vhd
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-- i2cBasics (Package for i2c basic modules)
-- Takashi Kohno (DigiCat)
-- Rev. 0.5.0c / 20, Jun., 2005
--
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t_regi2csm.vhd
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-- Test module for regI2cSlave and regI2cMaster
-- T.Kohno
-- Rev. 0.1.1c / 16, Jun., 2005
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t_regi2csm.vhd~
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-- Test module for regI2cSlave and regI2cMaster
-- T.Kohno
-- Rev. 0.1.1 / 16, Jun., 2005
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dac7615c.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DAC7615C is
Port ( ADC1 : in std_logic_vector(11 downto 0); --Channel1 input
dac902c.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dac902c is
Port ( clk : in std_logic;
reset : in std_logic;
clock_pkg.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package clock_pkg is
component hour is
port( hh,hl : buffer std_logic_vector (3 downto
clock.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.clock_pkg.all;
entity clock is
port( clk,clk2 : in std_logic ;
show: out
count.txt
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count is
port(clk:in std_logic;
reset:in std_logic;
on_off:in
count.vhd
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count is
port(clk:in std_logic;
reset:in std_logic;
on_off:in