clock.vhd.bak

基于VHDL的电子钟 实现一个简单的电子钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.clock_pkg.all;

entity clock is
port(  	clk,clk2 : in std_logic ;
		show: out std_logic_vector (6 downto 0);
		decode: buffer std_logic_vector (2 downto 0)
	);
end clock;
architecture clock_display of clock is
signal hourh,hourl,minh,minl,sech,secl: std_logic_vector( 3 downto 0);
signal c0:std_logic;
signal tempt: std_logic_vector (3 downto 0);
signal c1,c2: std_logic ;
begin
  		sec: cnt60 port map (sech,secl,clk,c1);
		min: cnt60 port map (minh,minl,c1,c2);
		hor: hour port map (hourh,hourl,c2);

  process(clk)
  begin
	if clk'event and clk='1' then 
		c0 <= not c0;
	end if;
  end process;

  process(clk2)
  begin 
  	if clk2'event and clk2 = '1' then
		case decode is
		when "110" => tempt <= hourh;
		when "111" => tempt <= hourl;
		when "000" => tempt <= "1111";
		when "001" => tempt <= minh;
		when "010" => tempt <= minl;
		when "011" => tempt <= "1111";
		when "100" => tempt <= sech;
		when "101" => tempt <= secl;
		end case ;
		
		decode <= decode+1;		---!!
	end if;
  end process;
  
  process(clk2)
  begin 
  	if clk2'event and clk2 = '1' then
		case tempt is
		when "0000" => show <= "1111110";	--led 0
		when "0001" => show <= "0110000";	--led 1
		when "0010" => show <= "1101101";	--led 2
		when "0011" => show <= "1111001";	--led 3
		when "0100" => show <= "0110011";	--led 4
		when "0101" => show <= "1011011";	--led 5
		when "0110" => show <= "1011111";	--led 6
		when "0111" => show <= "1110000";	--led 7
		when "1000" => show <= "1111111";	--led 8
		when "1001" => show <= "1111011";	--led 9
		when "1111" => show <= "0000001";	--led -
		when others => show <= "1111110";
		end case ;
	end if;
  end process;
 end architecture clock_display;