dac7615c.vhd

DesignWave 2005 8 Verilog Example

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity DAC7615C is
    Port ( ADC1 : in std_logic_vector(11 downto 0);	--Channel1 input
           ADC2 : in std_logic_vector(11 downto 0);	--Channel2 input
           ADC3 : in std_logic_vector(11 downto 0);	--Channel3 input
           ADC4 : in std_logic_vector(11 downto 0);	--Channel4 input
           RESET : in std_logic;								--reset active '1'
           CLK : in std_logic;								--10MHz(100ns)
           SDI : out std_logic;								--SDI output
           CLKn : out std_logic;								--/clock output
           CSn : out std_logic;								--/cs output
           LOADREGn : out std_logic;						--/loadreg output
           LOADDACS : out std_logic;						--100KHz(10us)
           RESETn : out std_logic;							--/reset output
           RESETSEL : out std_logic);						--refsetsel output
end DAC7615C;

architecture RTL of DAC7615C is

signal status :std_logic_vector(1 downto 0);				--"11":IDLE, "01":Shift, "10":Set, "00":Null
signal adr    :std_logic_vector(1 downto 0);				--DAC channel address
signal data   :std_logic_vector(11 downto 0);			--DAC data
signal sreg   :std_logic_vector(15 downto 0);			--Shift register [adr + "00" + data]		
signal cnt16  :std_logic_vector(3 downto 0);				--Internal counter 16
signal cnt4   :std_logic_vector(1 downto 0);				--Internal counter 4
signal loaddacs_node :std_logic;
signal cscnt  :std_logic_vector(6 downto 0);				--loadcs counter


begin

u_daccs_cnt:process(clk,reset)begin
	if(reset = '1')then
		cscnt <= (others => '0');
		loaddacs_node <= '0';
	elsif(clk'event and clk = '1')then
		if(cscnt = "1100100")then
			cscnt <= (others => '0');
			loaddacs_node <= '1';
		else
			cscnt <= cscnt + '1';
			loaddacs_node <= '0';
		end if;
	end if;
end process;

-------------------
-- State machine
-------------------
u_dac_status:process(clk, reset)begin
	if(reset = '1')then
		status <= "11";
		cnt16 <= "0000";
		cnt4 <= "00";
	elsif(clk'event and clk = '1')then
		case status is
			when "11" => --IDLE
				if(loaddacs_node = '1')then
					status <= "01";
				end if;
				cnt16 <= "0000";
				cnt4 <= "00";
			when "01" => --SHIFT
				if(cnt16 = "1111")then
					status <= "10";
					cnt16 <= "0000";
				else
					status <= "01";
					cnt16 <= cnt16 + '1';
				end if;
			when "10" => --SET
				if(cnt4 = "11")then
					status <= "11";
					cnt4 <= "00";
				else
					status <= "01";
					cnt4 <= cnt4 + '1';
				end if;
			when others =>
				status <= "11";
				cnt16 <= "0000";
				cnt4 <= "00";
		end case;
	end if;
end process;

----------------
-- Address controller
----------------
u_adr_cnt:process(clk,reset)begin
	if(reset = '1')then
		adr <= "00";
	elsif(clk'event and clk = '1')then
		if(status = "11")then
		   if(loaddacs_node = '1')then
		      adr <= "01";
		   else
			   adr <= "00";
			end if;
		elsif(status = "10")then
			adr <= adr + '1';
		end if;
	end if;
end process;

u_data_reg:process(clk,reset)begin
	if(reset = '1')then
		data <= "000000000000";
	elsif(clk'event and clk = '1')then
		case adr is
			when "00" =>
				data <= adc1;
			when "01" =>
				data <= adc2;
			when "10" =>
				data <= adc3;
			when others =>
				data <= adc4;
		end case;
	end if;
end process;
-------------------
-- Shift register
-------------------
u_shift_reg:process(clk,reset)begin
	if(reset = '1')then
		sreg <= (others => '0');
		sdi <= '0';
	elsif(clk'event and clk = '1')then
	   if(status = "11")then
	      if(loaddacs_node = '1')then
	          sreg <= adr & "00" & data;
	          sdi <= '0';
	      else
	         sreg <= (others => '0');
	         sdi <= '0';
	      end if;
		elsif(status = "10")then
			sreg <= adr & "00" & data;		--set
			sdi <= '0';
		elsif(status = "01")then					
			sreg <= sreg(14 downto 0) & '0';
			sdi <= sreg(15);
		end if;
	end if;
end process;


u_reg_cs_loadregn :process(clk,reset)begin
   if(reset = '1')then
        loadregn <= '1';
        csn <= '1';
   elsif(clk'event and clk = '1')then
      loadregn <= status(0);
      csn <= status(1);
   end if;
end process;
u_reg_loadcs: loaddacs <= not loaddacs_node;

resetsel <= '1';
resetn <= not reset;
clkn <= not clk;

end RTL;