clock_pkg.vhd.bak

基于VHDL的电子钟 实现一个简单的电子钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package clock_pkg is
	component hour is
	port( hh,hl : buffer std_logic_vector (3 downto 0);
      	  clk : in std_logic 
	);
	 end component ;
	
	component cnt60 is
	port(ch,cl : buffer std_logic_vector (3 downto 0);
      	 clk : in std_logic ;
		 carry: out std_logic   --?? buffer
	); 
	end component ;
end package ;