count.vhd

我的课程设计

library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity count is
  port(clk:in std_logic;
       reset:in std_logic;
       on_off:in std_logic;
       time10:in std_logic_vector(3 downto 0);
       time01:in std_logic_vector(3 downto 0);
       
       out10:out std_logic_vector(6 downto 0);
       out01:out std_logic_vector(6 downto 0);
       speaker:out std_logic );
end count;


architecture behave of count is

signal display10: std_logic_vector(3 downto 0);
signal display01: std_logic_vector(3 downto 0); 

begin
  process(clk,reset,on_off)
     begin
   if(on_off='1')then
     if(clk'event and clk='1')then
		if(reset='0')then
		
		display10<=time10;
		display01<=time01;
		else	
     if(display10/="0000")then
        if(display01="0000")then
         display01<="1001";
         display10<=display10-1;
        else
         display01<=display01-1;
        end if;
    else
        display01<=display01-1;
   end if;

   if(display01="0000" and display10="0000")then
      speaker<='1';
   else
     speaker<='0';
    end if;
end if;

if(display10/="0000")then
   
case display10 is
   when "0000" => out10<="0000001";--0   
   when "0001" => out10<="1001111";--1
   when "0010" => out10<="0010010";--2
   when "0011" => out10<="0000110";--3
   when "0100" => out10<="1001100"; --4
   when "0101" => out10<="0100100";--5
   when "0110" => out10<="0100000";--6
   when "0111" => out10<="0001111";--7
   when "1000" => out10<="0000000";--8
   when "1001" => out10<="0000100";--9
   when others => out10<="1111111";
  end case;

 case display01 is
       when "0000" => out01<="0000001";--0
       when "0101" => out01<="0100100";--5
       when others => out01<="1111111";
   end case;
else
  out10<="0000001";
  case display01 is
       when "0000" => out01<="0000001";--0   
       when "0001" => out01<="1001111";--1
       when "0010" => out01<="0010010";--2
       when "0011" => out01<="0000110";--3
       when "0100" => out01<="1001100"; --4
       when "0101" => out01<="0100100";--5
       when others => out01<="1111111";
   end case;
end if;

end if;
end if;
end process;
end behave;