t_regi2csm.vhd

DesignWave 2005 8 Verilog Example

--------------------------------------------------------------------------------
-- Test module for regI2cSlave and regI2cMaster
-- T.Kohno
-- Rev. 0.1.1c / 16, Jun., 2005
--------------------------------------------------------------------------------
library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;

use std.textio.all ;
use IEEE.std_logic_textio.all ;

use WORK.i2cCommon.all ;


entity TESTBNCH is
end TESTBNCH;

architecture stimulus of TESTBNCH is

component regI2cSlave
	generic( CKEDIVWIDTH		: integer := 4 ;
			 CKEDIV				: integer := 10
			 ) ;
	port(	CLK, nRST			: in std_logic ;
			
			-- Register I/F
			WrEn, RdEn			: in std_logic ;  -- Write Enable / Read Enable
			Usel				: in std_logic ;  -- Unit select
			Uadrs				: in std_logic_vector(2 downto 0) ;  -- Address in the Unit
			Din					: in std_logic_vector(7 downto 0) ;
			Dout				: out std_logic_vector(7 downto 0) ;
			Int					: out std_logic ;  -- Interruption output (level drive)

			-- i2c bus
			SCL, SDA			: in std_logic ;
			slvSCL, slvSDA		: out std_logic
			) ;
end component ;

component regI2cMaster
	generic( CKEDIVWIDTH		: integer := 4 ;
			 CKEDIV				: integer := 10
			 ) ;
	port(	CLK, nRST			: in std_logic ;
			
			-- Register I/F
			WrEn, RdEn			: in std_logic ;  -- Write Enable / Read Enable
			Usel				: in std_logic ;  -- Unit select
			Uadrs				: in std_logic_vector(2 downto 0) ;  -- Address in the Unit
			Din					: in std_logic_vector(7 downto 0) ;
			Dout				: out std_logic_vector(7 downto 0) ;
			Int					: out std_logic ;  -- Interruption output (level drive)

			-- i2c bus
			SCL, SDA			: in std_logic ;
			mstSCL, mstSDA		: out std_logic
			) ;
end component ;

component i2cRcv
	port(	CLK, nRST			: in std_logic ;
			CKE					: in std_logic ;  -- CLK enable for sampling clock
			
			-- i2c Bus
			SCL, SDA			: in std_logic ;
			
			-- i2cRcv I/F
			BoSCH				: out std_logic ;
			EoSCH				: out std_logic ;
			STAC				: out std_logic ;
			STPC				: out std_logic ;
			vSCL				: out std_logic ;
			vSDA				: out std_logic
			) ;
end component ;

component i2cDrv
	port(	CLK, nRST			: in std_logic ;
			CKE					: in std_logic ;  -- CLK enable for sampling clock
			
			-- i2c Bus
			SCLout, SDAout		: out std_logic ;

			-- from i2cRcv
			rcvSCL, rcvSDA		: in std_logic ;
			
			-- i2cDrv I/F
			BSY					: out std_logic ;
			gSTR				: in std_logic ;
			gDTR				: in std_logic ;
			gSTP				: in std_logic ;
			gRSR				: in std_logic ;
			Data				: in std_logic ;
			ABT					: in std_logic ;
			gDTW				: in std_logic ;

			Spre				: in std_logic_vector(3 downto 0) ;
			Spos				: in std_logic_vector(3 downto 0) ;
			Tlow				: in std_logic_vector(3 downto 0) ;
			Thig				: in std_logic_vector(3	downto 0) ;
			Dhol				: in std_logic_vector(1 downto 0)
			) ;
end component ;



constant SLAVEDELAY		: integer := 128 ;
constant MASTERDELAY	: integer := 256 ;

constant PERIOD: time := 30 ns;

signal CLK, nRST			: std_logic ;
signal CLKCount				: integer range -1 to 100000 ;

signal SCL, SDA		: std_logic ;

-- for regI2cSlave
signal SWrEn, SRdEn	: std_logic ;
signal SUsel		: std_logic ;
signal SUadrs		: std_logic_vector(2 downto 0) ;
signal SDin			: std_logic_vector(7 downto 0) ;
signal SDout		: std_logic_vector(7 downto 0) ;
signal SInt			: std_logic ;
signal slvSCL, slvSDA	: std_logic ;

-- for regI2cMaster
signal MWrEn, MRdEn	: std_logic ;
signal MUsel		: std_logic ;
signal MUadrs		: std_logic_vector(2 downto 0) ;
signal MDin			: std_logic_vector(7 downto 0) ;
signal MDout		: std_logic_vector(7 downto 0) ;
signal MInt			: std_logic ;
signal mstSCL, mstSDA	: std_logic ;


signal SSimCode, MSimCode		: integer ;
signal SWrData, MRdData			: std_logic_vector(7 downto 0) ;
signal mstData					: std_logic_vector(7 downto 0) ;

signal SlaveUnitReady			: std_logic ;

constant MessageLength			: integer := 10 ;
signal SlaveMessageString		: string(1 to MessageLength) ;
signal SlaveMessageValue		: std_logic_vector(7 downto 0) ;
signal SlaveMessageReq			: std_logic ;
signal SlaveMessageAck			: std_logic ;
signal MasterMessageString		: string(1 to MessageLength) ;
signal MasterMessageValue		: std_logic_vector(7 downto 0) ;
signal MasterMessageReq			: std_logic ;
signal MasterMessageAck			: std_logic ;


begin

-- component instantiation

	SDUT: regI2cSlave
		generic map ( CKEDIVWIDTH => 4,
					  CKEDIV => 4
					  )
		port map (	CLK => CLK, nRST => nRST,
					WrEn => SWrEn, RdEn => SRdEn,
					Usel => SUsel,
					Uadrs => SUadrs,
					Din => SDin,
					Dout => SDout,
					Int => SInt,
					SCL => SCL, SDA => SDA,
					slvSCL => slvSCL, slvSDA => slvSDA
					) ;

	MDUT: regI2cMaster
		generic map ( CKEDIVWIDTH => 4,
					  CKEDIV => 4
					  )
		port map (	CLK => CLK, nRST => nRST,
					WrEn => MWrEn, RdEn => MRdEn,
					Usel => MUsel,
					Uadrs => MUadrs,
					Din => MDin,
					Dout => MDout,
					Int => MInt,
					SCL => SCL, SDA => SDA,
					mstSCL => mstSCL, mstSDA => mstSDA
					) ;



	CLKGEN: process
        variable clktmp: std_logic := '0';
    begin
		CLK <= clktmp ;
        wait for PERIOD/2;
        clktmp := not clktmp;
    end process CLKGEN ;
    
	RSTGEN: process
	begin
		nRST <= '0' ;
		wait for PERIOD * 2 ;
		nRST <= '1' ;
		wait ;
	end process RSTGEN ;
	
    CLKCNT: process(CLK, nRST)
    begin
    	if nRST = '0' then
    		CLKCount <= 0 ;
    	elsif rising_edge(CLK) then
    		CLKCount <= CLKCount + 1 ;
    	end if ;
    end process ;




-- Simulation recorder
	SimRec: process
		file RecordFile			: text ;
		variable RecordLine		: line ;
		variable IndexString	: string(1 to 9) ;
	begin
		FILE_CLOSE(RecordFile) ;
		FILE_OPEN(RecordFile, "SimRecord.txt", WRITE_MODE) ;
		wait until nRST = '1' ;

		while nRST = '1' loop
			wait until SlaveMessageReq = '1' or MasterMessageReq = '1' ;
			if SlaveMessageReq = '1' then
				IndexString := "[Slave]  " ;
				WRITE(RecordLine, IndexString) ;
				WRITE(RecordLine, SlaveMessageString) ;
				HWRITE(RecordLine, SlaveMessageValue) ;
				WRITELINE(RecordFile, RecordLine) ;
				SlaveMessageAck <= '1' ;
				wait until SlaveMessageReq = '0' ;
				SlaveMessageAck <= '0' ;
			else
				IndexString := "[Master] " ;
				WRITE(RecordLine, IndexString) ;
				WRITE(RecordLine, MasterMessageString) ;
				HWRITE(RecordLine, MasterMessageValue) ;
				WRITELINE(RecordFile, RecordLine) ;
				MasterMessageAck <= '1' ;
				wait until MasterMessageReq = '0' ;
				MasterMessageAck <= '0' ;
			end if ;
		end loop ;
	end process ;


-- i2c bus
	SDA <= slvSDA and mstSDA ;
	SCL <= slvSCL and mstSCL ;


-- for regI2cSlave
	SlaveStim: process

		variable slvData		: std_logic_vector(7 downto 0) ;
		variable slvWrDelay		: std_logic ;

		procedure RegWrite(ADRS : in std_logic_vector(2 downto 0) ; DATA : in std_logic_vector(7 downto 0)) is
		begin
			SUsel <= '1' ;
			SUadrs <= ADRS ;
			SWrEn <= '1' ;
			SDin <= DATA ;
			wait until rising_edge(CLK) ;
			SWrEn <= '0' ;
			wait until rising_edge(CLK) ;
		end procedure ;

		procedure RegRead(ADRS : in std_logic_vector(2 downto 0)) is
		begin
			SUsel <= '1' ;
			SUadrs <= ADRS ;
			SRdEn <= '1' ;
			wait until rising_edge(CLK) ;
			SWrData <= SDout ;
			SRdEn <= '0' ;
			wait until rising_edge(CLK) ;
		end procedure ;

		procedure GetStatus is
		begin
			RegRead("000") ;
		end procedure ;

		procedure WriteCmnd(WCD : in std_logic_vector(7 downto 0)) is
		begin
			RegWrite("000", WCD) ;
		end procedure ;

		procedure ReadRData is
		begin
			RegRead("011") ;
		end procedure ;

		procedure WriteRData(WDD : in std_logic_vector(7 downto 0)) is
		begin
			RegWrite("011", WDD) ;
		end procedure ;

		procedure ReadWData is
		begin
			RegRead("010") ;
		end procedure ;

		procedure WriteWData is
		begin
			RegWrite("010", "00000000") ;
		end procedure ;

		procedure GetTrReg is
		begin
			RegRead("111") ;
		end procedure ;

		procedure WaitFor(WDD : in integer) is
		begin
			wait for PERIOD * 8 ;
			wait until rising_edge(CLK) ;
		end procedure ;

		procedure MessageRec is
		begin
			SlaveMessageReq <= '1' ;
			wait until SlaveMessageAck = '1' ;
			SlaveMessageReq <= '0' ;
			wait until SlaveMessageAck = '0' ;
		end procedure ;

		procedure MessageTrReg is
		begin
			GetTrReg ;
			SlaveMessageString <= "TrReg :   " ;
			SlaveMessageValue <= SWrData ;
			MessageRec ;
		end procedure ;

		procedure MessageStatus is
		begin
			GetStatus ;
			SlaveMessageString <= "Status:   " ;
			SlaveMessageValue <= SWrData ;
			MessageRec ;
		end procedure ;

		procedure MessageInt is
		begin
			SlaveMessageString <= "SInt:OK   " ;
			SlaveMessageValue <= (others => '0') ;
			MessageRec ;
		end procedure ;

		procedure MessageData is
		begin
			SlaveMessageString <= "SWrData:  " ;
			SlaveMessageValue <= SWrData ;
			MessageRec ;
		end procedure ;

		procedure MessageWriteRData is
		begin
			WriteRData(slvData) ;
			SlaveMessageString <= "SRdData:  " ;
			SlaveMessageValue <= slvData ;
			MessageRec ;
		end procedure ;
			
	begin
		SlaveUnitReady <= '0' ;
		SWrData <= (others => '0') ;
		slvData := "01011001" ;
		SSimCode <= 0 ;
		SWrEn <= '0' ;
		SRdEn <= '0' ;
		SUsel <= '0' ;
		SUadrs <= (others => '0') ;
		SDin <= (others => '0') ;
		slvWrDelay := '0' ;
		wait until nRST = '1' and rising_edge(CLK) ;
		wait until rising_edge(CLK) ;

		RegWrite("100", "00000011") ;  	-- Dsup = 3
		RegWrite("001", "00010111") ;  	-- Address = 17h
		RegWrite("111", "00000001") ;  	-- Int Enable
		

		WriteCmnd("00000111") ;  		-- Enable all the transactions
		
		WriteRData(slvData) ;  			-- Stack the first read data
		slvData := unsigned(slvData) + 1 ;
		
		SlaveUnitReady <= '1' ;
		
		while nRST = '1' loop
			wait until SInt = '1' ;
			MessageInt ;
			MessageTrReg ;		-- GetTrReg ;
			if SWrData(5) = '1' then
				case slvData is
					when X"5B" | X"60" | X"67" =>
					when X"5D" | X"68" | X"69" =>
						wait for PERIOD * SLAVEDELAY ;
						wait until rising_edge(CLK) ;
						WriteRData(slvData) ;
						SlaveMessageString <= "SRdData:* " ;
						SlaveMessageValue <= slvData ;
						MessageRec ;
						MessageTrReg ;
					when X"5E" | X"65" =>
						MessageWriteRData ;
						MessageTrReg ;
						slvData := unsigned(slvData) + 1 ;
						MessageStatus ;
						MessageWriteRData ;
						MessageTrReg ;
					when others =>
						MessageWriteRData ;
				end case ;
				slvData := unsigned(slvData) + 1 ;
			elsif SWrData(4) = '1' then
				if slvWrDelay = '1' then
					wait for PERIOD * SLAVEDELAY ;
					wait until rising_edge(CLK) ;
				end if ;
				ReadWData ;
				MessageData ;
				case SwrData is
					when X"36" =>
						WriteWData ;
						slvWrDelay := '0' ;
					when X"24" =>
						slvWrDelay := '1' ;
					when others =>
						slvWrDelay := '0' ;
				end case ;
			end if ;
			MessageStatus ;
		end loop ;
	end process ;