i2cbasics_package.vhd

DesignWave 2005 8 Verilog Example

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-- i2cBasics (Package for i2c basic modules)
-- Takashi Kohno (DigiCat)
-- Rev. 0.5.0c  / 20, Jun., 2005
--
----------------------------------------
--
-- Copyright (c)   2005   Takashi Kohno
-- This design is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or any later version.
--
-- This design is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
--
--------------------------------------------------------------------------------
library IEEE ;
use IEEE.std_logic_1164.all ;


package i2cBasics is
	type i2cBusState is (Pend, Free, STR, ATR, ACK, DTR, STP) ;

	component i2cDrv
		port(	CLK, nRST, syncRST	: in std_logic ;
				CKE					: in std_logic ;  -- CLK enable for sampling clock
			
				-- i2c Bus
				SCLout, SDAout		: out std_logic ;

				-- from i2cRcv
				rcvSCL, rcvSDA		: in std_logic ;

				-- i2cDrv I/F
				BSY					: out std_logic ;
				gSTR				: in std_logic ;
				gDTR				: in std_logic ;
				gSTP				: in std_logic ;
				gRSR				: in std_logic ;
				gDTW				: in std_logic ;
				Data				: in std_logic ;
				ABT					: in std_logic ;
				COL					: out std_logic ;

				Spre				: in std_logic_vector(3 downto 0) ;
				Spos				: in std_logic_vector(3 downto 0) ;
				Tlow				: in std_logic_vector(3 downto 0) ;
				Thig				: in std_logic_vector(3	downto 0) ;
				Dhol				: in std_logic_vector(1 downto 0)
				) ;
	end component ;

	component i2cRcv
		port(	CLK, nRST, syncRST	: in std_logic ;
				CKE					: in std_logic ;  -- CLK enable for sampling clock

				-- i2c Bus
				SCL, SDA			: in std_logic ;

				-- i2cRcv I/F
				BoSCH				: out std_logic ;
				EoSCH				: out std_logic ;
				STAC				: out std_logic ;
				STPC				: out std_logic ;
				vSCL				: out std_logic ;
				vSDA				: out std_logic
				) ;
	end component ;
	
	component i2cStDec
		port(	CLK, nRST, syncRST	: in std_logic ;
				CKE					: in std_logic ;  -- CLK enable for sampling clock

				-- i2c bus
				SCL, SDA			: in std_logic ;

				-- State Decoder outputs
				BSQ					: out i2cBusState ;  -- i2c Bus state
				BoSCH				: out std_logic ;  -- '1' for 1CLK at rising_edge(SCL)
				EoSCH				: out std_logic ;  -- '1' for 1CLK at falling_edge(SCL)
				STAC				: out std_logic ;  -- '1' for 1CLK at STArt Condition
				STPC				: out std_logic ;  -- '1' for 1CLK at SToP Condition
				ReceivedData		: out std_logic_vector(7 downto 0) ;
				FirstSBit			: out std_logic ;  -- '1' while processing the first serial bit
													   -- or nothing
				LastSBit			: out std_logic ;  -- '1' while processing the last serial bit
				vSCL, vSDA			: out std_logic ;  -- current status of SCL / SDA
				BFree				: out std_logic ;  -- '1' while i2c bus is free
				BObsc				: out std_logic  -- '1' while i2c bus status is unknown
				) ;
	end component ;

end i2cBasics ;