dac902c.vhd

DesignWave 2005 8 Verilog Example

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity dac902c is
    Port ( clk : in std_logic;
           reset : in std_logic;
           dout : in std_logic_vector(11 downto 0);
           dac : out std_logic_vector(11 downto 0);
           dacclk : out std_logic;
           pd : out std_logic);
end dac902c;

architecture rtl of dac902c is

begin

u_dac_reg :process(clk,reset)begin
	if(reset = '1')then
		dac <= "100000000000";
	elsif(clk'event and clk = '1')then
		dac <= not dout(11) & dout(10 downto 0);
	end if;
end process;

u_dacclk : dacclk <= not clk;

pd <= '1';

end rtl;