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Logic Analyzer 的代码
songer.vhd
LIBRARY IEEE; -- 硬件演奏电路顶层设计
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Songer IS
PORT ( CLK12MHZ : IN STD_LOGIC; --音调频率信号
-- CLK
speakera.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Speakera IS
PORT ( clk : IN STD_LOGIC;
Tone : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
songer.vhd
LIBRARY IEEE; -- 硬件演奏电路顶层设计
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Songer IS
PORT ( CLK12MHZ : IN STD_LOGIC; --音调频率信号
HIGH1 : OU
top.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TOP IS -- 顶层设计
PORT ( CLK12MHZ,HORL1 : IN STD_LOGIC;
INDEX1 : IN STD_LOGIC_VECTOR(6
top.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TOP IS -- 顶层设计
PORT ( CLK12MHZ,HORL1 : IN STD_LOGIC;
INDEX1 : IN STD_LOGIC_VECTOR(6
pci_io_virtex.vhd
--*****************************************************************************
--* *
--* EuCore PCI-T32 - PCI Ta
dct.vhd
---------------------------------------------------------------------------
-- Project: DCT
-- Revision: 1.0
-- Date of last Revision: October 2 1999
-- Designer: Vincenzo Liguori
-- Created
53_counter.vhd
library IEEE;
use IEEE.std_logic_1164.all;
package mycntpkg is
component count port(clk,rst : in std_logic;
cnt : inout std_logic_vector(2 downto 0));
end component;
end mycntpkg;
numdecoder.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity numdecoder is
port(
reset: in std_logic;
inclk: in std_logic;
innum: in st
cskz.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CSKZ IS
PORT(INA:IN STD_LOGIC;
OUTA:OUT STD_LOGIC);
END ENTITY CSKZ;
ARCHITECTURE ART OF CSKZ IS