songer.vhd

利用VHDL编写的电子琴发生器

LIBRARY IEEE; -- 硬件演奏电路顶层设计
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Songer IS                                    
    PORT (   CLK12MHZ : IN STD_LOGIC;             --音调频率信号         
--             CLK8HZ : IN STD_LOGIC;               --节拍频率信号
               CODE3  : OUT iNTEGER RANGE 0 TO 15;-- 简谱码输出显示
               HIGH2  : OUT STD_LOGIC; --高8度指示
             SPKOUT2  : OUT STD_LOGIC );--声音输出
 END;
ARCHITECTURE one OF Songer IS
   COMPONENT NoteTabs
     PORT ( clk    : IN STD_LOGIC;
         ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );
    END COMPONENT;
    COMPONENT ToneTaba
        PORT ( Index :  IN  STD_LOGIC_VECTOR (3 DOWNTO 0) ;
               CODE  : OUT  iNTEGER RANGE 0 TO 15;
               HIGH  : OUT STD_LOGIC; 
               Tone  : OUT  STD_LOGIC_VECTOR (10 DOWNTO 0) );
    END COMPONENT;
    COMPONENT Speakera
        PORT  ( clk  : IN STD_LOGIC;
                Tone : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
                SpkS : OUT STD_LOGIC  );
    END COMPONENT;
    SIGNAL Tone : STD_LOGIC_VECTOR (10 DOWNTO 0);
    SIGNAL ToneIndex : STD_LOGIC_VECTOR (3 DOWNTO 0); 
	SIGNAL CLK8HZ   : STD_LOGIC;               --节拍频率信号
	SIGNAL CODE1  :  INTEGER RANGE 0 TO 15;-- 简谱码输出显示
 BEGIN
u1 : NoteTabs  PORT MAP (clk=>CLK8HZ, ToneIndex=>ToneIndex);
u2 : ToneTaba PORT MAP (Index=>ToneIndex,Tone=>Tone,CODE=>CODE3,HIGH=>HIGH2);
u3 : Speakera PORT MAP(clk=>CLK12MHZ,Tone=>Tone, SpkS=>SPKOUT2 );
PROCESS(CLK12MHZ)
	VARIABLE count8Hz : INTEGER RANGE 0 TO 750010:=0;
BEGIN
	IF(CLK12MHZ'EVENT AND CLK12MHZ='1') THEN
		IF count8Hz>=750000 THEN 
			count8Hz:=0;
			CLK8HZ<= NOT CLK8HZ;
			ELSE  count8Hz:=count8Hz+1;
		END IF;	
	END IF;
END PROCESS;
END;