pci_io_virtex.vhd

VHDL编写的PCI代码,PCI2.2兼容,Xillinx Virtex与Spantan II 优化,33M主频,32位宽度,全目标功能等.

--*****************************************************************************
--*                                                                           *
--*            EuCore PCI-T32 - PCI Target Interface Core                     *
--*            (C)2000 MaxLock, Inc. All rights reserved                      *
--*                                                                           *
--*****************************************************************************
-- FILE    : PCI_IO_Virtex
-- DATE    : 10.1.2001
-- REVISION: 1.1
-- DESIGNER: Tony
-- Descr   : Physical I/O Interface to PCI Pins for VIRTEX family
-- Entities: PCI_IO_Virtex
--           PCILOGIC
-- Changes :
-- ******************************************************
-- *    Physical I/O Interface Entity                   *
-- ******************************************************
library IEEE;
use IEEE.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity PCI_IO_Virtex is
  port (
      -- ## PCI Interface External Signals ## --
      RSTn_p     : in    std_logic;                     -- Reset	
      CLK_p      : in    std_logic;                     -- Clock	
       -- Address & Data 
      AD_p       : inout std_logic_vector(31 downto 0); -- Address/Data Bus
      CBE_p      : in std_logic_vector(3 downto 0);  -- Command/Byte Enable
      PAR_p      : inout std_logic;                     -- Parity
      -- Interface Control
      FRAMEn_p   : in std_logic;                     -- Transaction Frame
      IRDYn_p    : in std_logic;                     -- Initiator Ready
      TRDYn_p    : inout std_logic;                     -- Target Ready
      DEVSELn_p  : inout std_logic;                     -- Device Select
      STOPn_p    : inout std_logic;                     -- Stop transaction
      IDSEL_p    : in    std_logic;                     -- Chip Select
      -- Error Reporting
      PERRn_p    : inout   std_logic;                   -- Parity Error (s/t/s)
      SERRn_p    : inout   std_logic;                   -- System Error (o/d)
      -- Interrupt
      INTAn_p    : out   std_logic;                     -- Interrupt pin (o/d)
      --### SYSTEM I/F Signals
      RESET      : out std_logic;                        -- Chip Reset
      CLK        : out std_logic;                        -- Chip Clock		    	
      -- Address & Data 
      ADi        : out std_logic_vector(31 downto 0);    -- Address/Data Bus  IN
      ADo        : in  std_logic_vector(31 downto 0);    -- Address/Data Bus  OUT
      CBEi       : out std_logic_vector(3 downto 0);     -- Command/Byte Enable Direct IN
      CBEid      : out std_logic_vector(3 downto 0);     -- Command/Byte Enable Registered IN
      PARi       : out std_logic;              -- Parity In  (-> Board)
      PARid      : out std_logic;              -- Parity In  (-> Board)
      PARo       : in  std_logic;                        -- Parity Out (Board ->)
      --### System Control signals
      -- Direct PCI Inputs
      IDSELi      : out std_logic;
      FRAMEni     : out std_logic;
      IRDYni      : out std_logic;
      DEVSELni    : out std_logic;
      TRDYni      : out std_logic;
      STOPni      : out std_logic;
      -- Registered PCI Inputs
      IDSELid     : out std_logic;
      FRAMEnid    : out std_logic;
      IRDYnid     : out std_logic;
      DEVSELnid   : out std_logic;
      TRDYnid     : out std_logic;
      STOPnid     : out std_logic;
      -- PCI Outputs
      NEW_DEVSELno: in  std_logic;
      NEW_TRDYno  : in  std_logic;
      NEW_STOPno  : in  std_logic;
      -- Tristate buffer control
      OT_DEVSEL   : in  std_logic; 
      OT_TRDY     : in  std_logic; 
      OT_STOP     : in  std_logic;
      T_OT_AD     : in  std_logic; 	-- Target DATA Output Tristate control
      CE_ADo      : in  std_logic;
      T_CE_ADoRDY : in  std_logic;

      -- Interrupt
      INTAno      : in   std_logic; -- Interrupt 
      -- Error Reporting
      PERRni      : out   std_logic; -- Parity Error In
      SERRni      : out   std_logic; -- System Error In
      PERRnid     : out   std_logic; -- Parity Error In
      SERRnid     : out   std_logic; -- System Error In
      NEW_PERRno  : in   std_logic;  -- Parity Error Out
      NEW_OTPERR  : in   std_logic;  -- Parity Error Buffer Control
      NEW_SERRno  : in   std_logic  -- System Error Out
   );
  end PCI_IO_Virtex;
-- 
library ieee;
use ieee.std_logic_1164.all;
entity PCILOGIC is
    port (PCI_CE : out std_logic; 
          IRDY   : in  std_logic;
          T_CE_RDY   : in  std_logic;
          DIR_CEo : in  std_logic
          );
end PCILOGIC;

-- 
-- 
architecture Struct of PCI_IO_Virtex is
   component FDCE is
      generic(
      TimingChecksOn: Boolean := FALSE);
      port(
      Q   :	out   std_logic;
      D   :	in    std_logic;
      C   :	in    std_logic;
      CE  :	in    std_logic;
      CLR :	in    std_logic);
  end component;
  component FDPE is
      generic(
      TimingChecksOn: Boolean := FALSE);
    port(
      Q   :	out   std_logic;
      D   :	in    std_logic;
      C   :	in    std_logic;
      CE  :	in    std_logic;
      PRE :	in    std_logic
    );end component;
  component IBUF is
     port(
         I: in std_logic;
         O: out std_logic
     ); end component;
  component BUFGP is
     port(
         I: in std_logic;
         O: out std_logic
     ); end component;
  component OBUF is
     port(
         I: in std_logic;
         O: out std_logic
     ); end component;
  component OBUFT is
     port(
         I: in std_logic;
         O: out std_logic;
         T: in std_logic
     ); end component; 
   component PCILOGIC 
      port (
      PCI_CE: out std_logic;
      IRDY  : in  std_logic;
      T_CE_RDY: in  std_logic;
      DIR_CEo : in  std_logic
      );
   end component;        
	-- Component declaration of the GEN_PAR unit
	-- File name contains GEN_PAR entity: .\G_PARITY.vhd
	component GEN_PAR
	port(
		RESET : in std_logic;
		CLK : in std_logic;
		CE_ADo : in std_logic;
		ADo : in std_logic_vector(31 downto 0);
		CBEi : in std_logic_vector(3 downto 0);
		NEW_PARo : out std_logic);
	end component;

   -- local signals
   signal CLKi, RESETn,RESETi : std_logic;  
   signal IDSELil: std_logic;  
   signal IRDYnil:  std_logic;  
   signal TRDYnil:  std_logic;  
   signal FRAMEnil:  std_logic;
   signal STOPnil: std_logic; 
   signal LPARi: std_logic;
   signal DEVSELnil: std_logic; 
   signal LGNTni  : std_logic;