dct.vhd

这是用VHDL语言(硬件描述语言)写的一个二维 8*8块的离散余弦变换(DCT)以及反变换(IDCT).全同步设计,低门数.可以用于多媒体及打印应用领域.

---------------------------------------------------------------------------
-- Project: DCT 
-- Revision: 1.0 
-- Date of last Revision: October 2 1999 
-- Designer: Vincenzo Liguori 
-- Created by Xentec Inc. 
-- Copyright (c) 1995-1999 Xentec Inc. & Ocean Logic Pty Ltd 
-- Please review the terms of the license agreement before using this file. 
-- If you are not an authorized user, please destroy this source code file 
-- and notify Xentec, Inc. immediately that you inadvertently received an 
-- unauthorized copy. 1 888 7 XENTEC x22 
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dct is port(
  -- Inputs
  clk, res_n : in std_logic;
  start, en, idct : in std_logic;
  xh : in std_logic_vector(10 downto 0);
  xv : in std_logic_vector(13 downto 0);
  -- Outputs
  yh : out std_logic_vector(13 downto 0);
  yv : out std_logic_vector(11 downto 0);
  memh, memv : out std_logic_vector(5 downto 0);
  ready : out std_logic );
end dct;

architecture rtl of dct is

  component addr_gen port(
    -- Inputs
    clk, res_n : in std_logic;
    en, start, idct : in std_logic;
    -- Outputs
    sgn1, sgn2, sgn3, sgn4, sgn5, sgn6, sgn7, load : out std_logic;
    slx2, sli0, sli1, sli2 : out std_logic;
    slx40, slx41, slx42, slx43 : out std_logic_vector(1 downto 0);
    memh, memv : out std_logic_vector(5 downto 0);
    ready : out std_logic);
  end component;
  
  component mulh port(
    clk, res_n : std_logic;
    en, idct : in std_logic;
    xin : in std_logic_vector(10 downto 0);
    y0, y1, y2, y3, y5, y6, y7 : out std_logic_vector(12 downto 0));
  end component;
  
  component crossh port(
    y0, y1, y2, y3, y5, y6, y7 : in std_logic_vector(12 downto 0);
    idct, slx2, sli0, sli1, sli2 : in std_logic;
    slx40, slx41, slx42, slx43 : in std_logic_vector(1 downto 0);
    sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7 : out std_logic_vector(12 downto 0));
  end component;
  
  component acch port(
    clk, res_n : in std_logic;
    en : in std_logic;
    sgn1, sgn2, sgn3, sgn4, sgn5, sgn6, sgn7, load : in std_logic;
    sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7 : in std_logic_vector(12 downto 0);
    y : out std_logic_vector(13 downto 0));
  end component;
  
  component mulv port(
    idct : in std_logic;
    xin : in std_logic_vector(13 downto 0);
    y0, y1, y2, y3, y5, y6, y7 : out std_logic_vector(12 downto 0));
    end component;
  
  component crossv port(
    y0, y1, y2, y3, y5, y6, y7 : in std_logic_vector(12 downto 0);
    idct, slx2, sli0, sli1, sli2 : in std_logic;
    slx40, slx41, slx42, slx43 : in std_logic_vector(1 downto 0);
    sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7 : out std_logic_vector(12 downto 0));
  end component;
  
  component accv port(
    clk, res_n : in std_logic;
    en : in std_logic;
    sgn1, sgn2, sgn3, sgn4, sgn5, sgn6, sgn7, load : in std_logic;
    sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7 : in std_logic_vector(12 downto 0);
    y : out std_logic_vector(11 downto 0));
  end component;

  signal sgn1, sgn2, sgn3, sgn4, sgn5, sgn6, sgn7, load : std_logic;
  signal slx2, sli0, sli1, sli2 : std_logic;
  signal slx40, slx41, slx42, slx43 : std_logic_vector(1 downto 0);
  signal yh0, yh1, yh2, yh3, yh5, yh6, yh7 : std_logic_vector(12 downto 0);
  signal selh0, selh1, selh2, selh3, selh4, selh5, selh6, selh7 : std_logic_vector(12 downto 0);
  signal yv0, yv1, yv2, yv3, yv5, yv6, yv7 : std_logic_vector(12 downto 0);
  signal selv0, selv1, selv2, selv3, selv4, selv5, selv6, selv7 : std_logic_vector(12 downto 0);

begin

  adr : addr_gen port map(
    clk => clk,
    res_n => res_n,
    en => en,
    start => start,
    idct => idct,
    sgn1 => sgn1,
    sgn2 => sgn2,
    sgn3 => sgn3,
    sgn4 => sgn4,
    sgn5 => sgn5,
    sgn6 => sgn6,
    sgn7 => sgn7,
    load => load,
    slx2 => slx2,
    sli0 => sli0,
    sli1 => sli1,
    sli2 => sli2,
    slx40 => slx40,
    slx41 => slx41,
    slx42 => slx42,
    slx43 => slx43,
    memh => memh,
    memv => memv, 
    ready => ready );
    
  mlh : mulh port map(
    -- Inputs
    clk => clk,
    res_n => res_n,
    en => en,
    idct => idct,
    xin => xh,
    -- Outputs
    y0 => yh0,
    y1 => yh1,
    y2 => yh2,
    y3 => yh3,
    y5 => yh5,
    y6 => yh6,
    y7 => yh7);
    
  crh : crossh port map(
    -- Inputs
    y0 => yh0,
    y1 => yh1,
    y2 => yh2,
    y3 => yh3,
    y5 => yh5,
    y6 => yh6,
    y7 => yh7,
    idct => idct,
    slx2 => slx2,
    sli0 => sli0,
    sli1 => sli1,
    sli2 => sli2,
    slx40 => slx40,
    slx41 => slx41,
    slx42 => slx42,
    slx43 => slx43,
    -- Outputs
    sel0 => selh0,
    sel1 => selh1,
    sel2 => selh2,
    sel3 => selh3,
    sel4 => selh4,
    sel5 => selh5,
    sel6 => selh6,
    sel7 => selh7);

  ach : acch port map(
    -- Inputs
    clk => clk,
    res_n => res_n,
    en => en,
    sgn1 => sgn1,
    sgn2 => sgn2,
    sgn3 => sgn3,
    sgn4 => sgn4,
    sgn5 => sgn5,
    sgn6 => sgn6,
    sgn7 => sgn7,
    load => load,
    sel0 => selh0,
    sel1 => selh1,
    sel2 => selh2,
    sel3 => selh3,
    sel4 => selh4,
    sel5 => selh5,
    sel6 => selh6,
    sel7 => selh7,
    -- Outputs
    y => yh );
    
  mlv : mulv port map(
    -- Inputs
    idct => idct,
    xin => xv,
    -- Outputs
    y0 => yv0,
    y1 => yv1,
    y2 => yv2,
    y3 => yv3,
    y5 => yv5,
    y6 => yv6,
    y7 => yv7 );
    
  crv : crossv port map(
    -- Inputs
    y0 => yv0,
    y1 => yv1,
    y2 => yv2,
    y3 => yv3,
    y5 => yv5,
    y6 => yv6,
    y7 => yv7,
    idct => idct,
    slx2 => slx2,
    sli0 => sli0,
    sli1 => sli1,
    sli2 => sli2,
    slx40 => slx40,
    slx41 => slx41,
    slx42 => slx42,
    slx43 => slx43,
    -- Outputs
    sel0 => selv0,
    sel1 => selv1,
    sel2 => selv2,
    sel3 => selv3,
    sel4 => selv4,
    sel5 => selv5,
    sel6 => selv6,
    sel7 => selv7);
    
  acv : accv port map(
    -- Inputs
    res_n => res_n,
    clk => clk,
    en => en,
    sgn1 => sgn1,
    sgn2 => sgn2,
    sgn3 => sgn3,
    sgn4 => sgn4,
    sgn5 => sgn5,
    sgn6 => sgn6,
    sgn7 => sgn7,
    load => load,
    sel0 => selv0,
    sel1 => selv1,
    sel2 => selv2,
    sel3 => selv3,
    sel4 => selv4,
    sel5 => selv5,
    sel6 => selv6,
    sel7 => selv7,
    -- Outputs
    y => yv);
 
end rtl;