top.vhd

利用VHDL编写的电子琴发生器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TOP IS                                     -- 顶层设计
    PORT (   CLK12MHZ,HORL1 : IN STD_LOGIC;
               INDEX1       : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
               CODE1        : OUT INTEGER RANGE 0 TO 15;
               HIGH1        : OUT STD_LOGIC; 
               NUME1        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
              SPKOUT        : OUT STD_LOGIC );
 END;
ARCHITECTURE one OF TOP IS
       COMPONENT Tone
         PORT ( Index : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
                CODE  : OUT INTEGER RANGE 0 TO 15;
                HIGH  : OUT STD_LOGIC; 
                HORL  : IN  STD_LOGIC; 
                NUME  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                Tone  : OUT INTEGER RANGE 0 TO 16#7FF#  ); --11位2进制数
    END COMPONENT;
    COMPONENT Speaker
        PORT (  clk1  :  IN STD_LOGIC;
                Tone1 :  IN INTEGER RANGE 0 TO 16#7FF#;          --11位2进制数
                 SpkS : OUT STD_LOGIC  );
    END COMPONENT;
    SIGNAL Tone2 : INTEGER RANGE 0 TO 16#7FF#;
  BEGIN                    -- 安装U1, U2
u1 : Tone    PORT MAP (Index=>Index1, Tone=>Tone2,CODE=>CODE1,
                        HIGH=>HIGH1,HORL=>HORL1,NUME=>NUME1);
u2 : Speaker PORT MAP (clk1=>CLK12MHZ,Tone1=>Tone2, SpkS=>SPKOUT );
END;





LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Tone IS
    PORT ( Index :  IN STD_LOGIC_VECTOR(6 DOWNTO 0);
           HORL  :  IN STD_LOGIC; 
           CODE  : OUT INTEGER RANGE 0 TO 15;
           NUME  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
           HIGH  : OUT STD_LOGIC; 
           Tone  : OUT INTEGER RANGE 0 TO 16#7FF#  );
END;
ARCHITECTURE one OF Tone IS
   SIGNAL KLK :  STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
   PROCESS(HORL)
     BEGIN
        IF HORL'EVENT AND HORL = '1' THEN      KLK <= KLK + 1;   
                  END IF;
          NUME <= '0'&'0'& KLK; 
   END PROCESS;     
    Search : PROCESS(Index)
    BEGIN
        IF KLK = "00" THEN
        CASE Index IS       -- 译码电路，查表方式，控制音调的预置数
            WHEN "0000001"  => Tone <= 773;  CODE <= 1; HIGH <= '0';  
            WHEN "0000010"  => Tone <= 912;  CODE <= 2; HIGH <= '0';  
            WHEN "0000100"  => Tone <= 1036; CODE <= 3; HIGH <= '0'; 
            WHEN "0001000"  => Tone <= 1116; CODE <= 4; HIGH <= '0'; 
            WHEN "0010000"  => Tone <= 1197; CODE <= 5; HIGH <= '0';  
            WHEN "0100000"  => Tone <= 1290; CODE <= 6; HIGH <= '0';  
            WHEN "1000000"  => Tone <= 1372; CODE <= 7; HIGH <= '0';  
            WHEN   OTHERS    => Tone <= 2047; CODE <= 0; HIGH <= '0';  
        END CASE;
        ELSIF KLK = "01" THEN
        CASE Index IS       -- 译码电路，查表方式，控制音调的预置数
            WHEN "0000001"  => Tone <= 1410;  CODE <= 1; HIGH <= '1';  
            WHEN "0000010"  => Tone <= 1490;  CODE <= 2; HIGH <= '1'; 
            WHEN "0000100"  => Tone <= 1560;  CODE <= 3; HIGH <= '1'; 
            WHEN "0001000"  => Tone <= 1600;  CODE <= 4; HIGH <= '1';  
            WHEN "0010000"  => Tone <= 1622; CODE  <= 5; HIGH <= '1';  
            WHEN "0100000"  => Tone <= 1650;  CODE <= 6; HIGH <= '1';  
            WHEN "1000000"  => Tone <= 1690;  CODE <= 7; HIGH <= '1';  
            WHEN   OTHERS    => Tone <= 2047; CODE <= 0; HIGH <= '1'; 
        END CASE;
       ELSIF KLK = "10" THEN
        CASE Index IS       -- 译码电路，查表方式，控制音调的预置数
            WHEN "0000001"  => Tone <= 1730;  CODE <= 1; HIGH <= '1'; 
            WHEN "0000010"  => Tone <= 1750;  CODE <= 2; HIGH <= '1'; 
            WHEN "0000100"  => Tone <= 1770;  CODE <= 3; HIGH <= '1'; 
            WHEN "0001000"  => Tone <= 1790;  CODE <= 4; HIGH <= '1';  
            WHEN "0010000"  => Tone <= 1815; CODE  <= 5; HIGH <= '1';  
            WHEN "0100000"  => Tone <= 1830;  CODE <= 6; HIGH <= '1';  
            WHEN "1000000"  => Tone <= 1930;  CODE <= 7; HIGH <= '1';  
            WHEN   OTHERS    => Tone <= 2047; CODE <= 0; HIGH <= '1'; 
        END CASE;
        ELSE
            CASE Index IS       -- 译码电路，查表方式，控制音调的预置数
            WHEN "0000001"  => Tone <= 100;  CODE <= 1; HIGH <= '1';  
            WHEN "0000010"  => Tone <= 200;  CODE <= 2; HIGH <= '1'; 
            WHEN "0000100"  => Tone <= 300;  CODE <= 3; HIGH <= '1'; 
            WHEN "0001000"  => Tone <= 400;  CODE <= 4; HIGH <= '1';  
            WHEN "0010000"  => Tone <= 500;  CODE <= 5; HIGH <= '1';  
            WHEN "0100000"  => Tone <= 600;  CODE <= 6; HIGH <= '1';  
            WHEN "1000000"  => Tone <= 700;  CODE <= 7; HIGH <= '1';  
            WHEN   OTHERS    => Tone <= 2047; CODE <= 0; HIGH <= '1'; 
        END CASE;
      END IF;
    END PROCESS;
END;



LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Speaker IS
    PORT (  clk1   : IN STD_LOGIC;
             Tone1 : IN INTEGER RANGE 0 TO 16#7FF#;
             SpkS  : OUT STD_LOGIC  );
END;
ARCHITECTURE one OF Speaker IS
    SIGNAL   PreCLK , FullSpkS : STD_LOGIC;
    BEGIN
 DivideCLK : PROCESS(clk1)
        VARIABLE Count4 : INTEGER RANGE 0 TO 15;
    BEGIN
        PreCLK <= '0';       -- 将CLK进 11分频，PreCLK为C L 11K 6分频
        IF Count4 > 11  THEN  
            PreCLK <= '1';
            Count4 := 0;
        ELSIF clk1'EVENT AND clk1 = '1' THEN
            Count4 := Count4 + 1;            
        END IF;
    END PROCESS;
    GenSpkS : PROCESS(PreCLK, Tone1)
        VARIABLE Count11 : INTEGER RANGE 0 TO 16#7FF#;
BEGIN            -- 11位可预置计数器
        IF PreCLK'EVENT AND PreCLK = '1' THEN
            IF   Count11 = 16#7FF# THEN
                Count11 := Tone1;
                FullSpkS <= '1';                
            ELSE
                Count11 := Count11 + 1;
                FullSpkS <= '0';                
            END IF;
        END IF;
        END PROCESS;
    DelaySpkS : PROCESS(FullSpkS)
        VARIABLE Count2 : STD_LOGIC;
        BEGIN               -- 将输出再进行2分频，将脉冲展宽，以使扬声器有足够功率发音
        IF FullSpkS'EVENT AND FullSpkS = '1' THEN
            Count2 := NOT Count2;
            IF Count2 = '1' THEN  SpkS <= '1';
            ELSE                  SpkS <= '0';
            END IF;
        END IF;
        END PROCESS;
        END;