numdecoder.vhd

用VHDL语言实现通用计算器设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity numdecoder is
port(
	reset: in std_logic;
	inclk: in std_logic;
	innum: in std_logic_vector( 9 downto 0);
	outnum: buffer std_logic_vector(3 downto 0);
	outflag: out std_logic
);
end numdecoder;

architecture decoder of numdecoder is

begin
process(inclk,reset)
begin
if reset='1' then
outnum<="0000";
elsif inclk'event and inclk='1' then
case innum is
when "0000000001"=>outnum<="0000";outflag<='1';
when "0000000010"=>outnum<="0001";outflag<='1';
when "0000000100"=>outnum<="0010";outflag<='1';
when "0000001000"=>outnum<="0011";outflag<='1';
when "0000010000"=>outnum<="0100";outflag<='1';
when "0000100000"=>outnum<="0101";outflag<='1';
when "0001000000"=>outnum<="0110";outflag<='1';
when "0010000000"=>outnum<="0111";outflag<='1';
when "0100000000"=>outnum<="1000";outflag<='1';
when "1000000000"=>outnum<="1001";outflag<='1';
when others=> outnum<=outnum;outflag<='0';
end case;
end if;
end process;
end decoder;