songer.vhd

来自「利用VHDL编写的电子琴发生器」· VHDL 代码 · 共 40 行

LIBRARY IEEE; -- 硬件演奏电路顶层设计
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Songer IS                                    
    PORT (   CLK12MHZ : IN STD_LOGIC;             --音调频率信号 
               HIGH1  : OUT STD_LOGIC; --高8度指示
             SPKOUT   : OUT STD_LOGIC );--声音输出
 END;
ARCHITECTURE one OF Songer IS
   COMPONENT NoteTabs
     PORT ( clk    : IN STD_LOGIC;
         ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );
    END COMPONENT;
    COMPONENT ToneTaba
        PORT ( Index :  IN  STD_LOGIC_VECTOR (3 DOWNTO 0) ;
               HIGH  : OUT STD_LOGIC; 
               Tone  : OUT  STD_LOGIC_VECTOR (10 DOWNTO 0) );
    END COMPONENT;
    COMPONENT Speakera
        PORT  ( clk  : IN STD_LOGIC;
                Tone : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
                SpkS : OUT STD_LOGIC  );
    END COMPONENT;
signal clk8hz:std_logic;
    SIGNAL Tone : STD_LOGIC_VECTOR (10 DOWNTO 0);
    SIGNAL ToneIndex : STD_LOGIC_VECTOR (3 DOWNTO 0); 
 BEGIN
u1 : NoteTabs  PORT MAP (clk=>CLK8HZ, ToneIndex=>ToneIndex);
u2 : ToneTaba PORT MAP (Index=>ToneIndex,Tone=>Tone,HIGH=>HIGH1);
u3 : Speakera PORT MAP(clk=>CLK12MHZ,Tone=>Tone, SpkS=>SPKOUT );
process(clk12mhz)
variable count12to8: integer range 0 to 750010:=0;
begin 
if CLK12MHZ'event and CLK12MHZ='1' then 
if  count12to8>=750000 then count12to8:=0; 
clk8hz<=not clk8hz;
else count12to8:=count12to8+1;
end if;
end if;
end process;
END;